Presentation on theme: "1 EE365 Sequential-circuit analysis. 2 Clocked synchronous seq. circuits A.k.a. “state machines” Use edge-triggered flip-flops All flip-flops are triggered."— Presentation transcript:
1 EE365 Sequential-circuit analysis
2 Clocked synchronous seq. circuits A.k.a. “state machines” Use edge-triggered flip-flops All flip-flops are triggered from the same master clock signal, and therefore all change state together Feedback sequential circuits –No explicit flip-flops; state stored in feedback loops –Example: edge-triggered D flip-flop itself (4 states) –Sections 7.9, 7.10 (advanced courses)
3 State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input
4 State-machine structure (Moore) output depends on state only typically edge-triggered D flip-flops
5 State-machine structure (pipelined) Often used in PLD-based state machines. –Outputs taken directly from flip-flops, valid sooner after clock edge. –But the “output logic” must determine output value one clock tick sooner (“pipelined”).
6 Notation, characteristic equations Q means “the next value of Q.” “Excitation” is the input applied to a device that determines the next state. “Characteristic equation” specifies the next state of a device as a function of its excitation. S-R latch: Q = S + R´ · Q Edge-triggered D flip-flop: Q = D
7 State-machine analysis steps Assumption: Starting point is a logic diagram. 1. Determine next-state function F and output function G. 2a. Construct state table –For each state/input combination, determine the excitation value. –Using the characteristic equation, determine the corresponding next-state values (trivial with D f-f’s). 2b. Construct output table –For each state/input combination, determine the output value. (Can be combined with state table.) 3. (Optional) Draw state diagram