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Overview of Chapter 5 °Circuits require memory to store intermediate data °Sequential circuits use a periodic signal to determine when to store values.

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Presentation on theme: "Overview of Chapter 5 °Circuits require memory to store intermediate data °Sequential circuits use a periodic signal to determine when to store values."— Presentation transcript:

1 Overview of Chapter 5 °Circuits require memory to store intermediate data °Sequential circuits use a periodic signal to determine when to store values. A clock signal can determine storage times Clock signals are periodic °Single bit storage element is a flip flop °A basic type of flip flop is a latch °Latches are made from logic gates NAND, NOR, AND, OR, Inverter

2 The story so far... °Logical operations which respond to combinations of inputs to produce an output. Call these combinational logic circuits. °For example, can add two numbers. But: No way of adding two numbers, then adding a third (a sequential operation); No way of remembering or storing information after inputs have been removed. °To handle this, we need sequential logic capable of storing intermediate (and final) results.

3 Sequential Circuits Combinational circuit Flip Flops Outputs Inputs Next state Present state Timing signal (clock) Clock a periodic external event (input) Clock a periodic external event (input) synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems

4 Cross-coupled Inverters State 1 State 2 °A stable value can be stored at inverter outputs

5 S-R Latch with NORs S R Q Q’ Set 1 0 Stable 0 1 Reset 0 0 Undefined R (reset) Q Q S (set) °S-R latch made from cross-coupled NORs °If Q = 1, set state °If Q = 0, reset state °Usually S=0 and R=0 °S=1 and R=1 generates unpredictable results

6 S-R Latch with NANDs S R Q Q’ S R Q Q’ Set 1 0 Store 0 1 Reset 1 1 Disallowed °Latch made from cross-coupled NANDs °Sometimes called S’-R’ latch °Usually S=1 and R=1 °S=0 and R=0 generates unpredictable results

7 S-R Latches

8 S-R Latch with control input °Occasionally, desirable to avoid latch changes °C = 0 disables all latch state changes °Control signal enables data change when C = 1 °Right side of circuit same as ordinary S-R latch.

9 Latch operation enabled by C C Input sampling enabled by gates NOR S-R Latch with Control Input R’ S’ Q’ Q C’ Outputs change when C is low: RESET and SET Otherwise: HOLD Outputs change when C is low: RESET and SET Otherwise: HOLD Latch is level-sensitive, in regards to C Only stores data if C’ = 0

10 D Latch Q Q’ C D S R X Y X Y C Q Q’ Q 0 Q 0 ’ Store Reset Set Disallowed X X 0 Q 0 Q 0 ’ Store X 0 Q 0 Q 0 ’ D C Q Q’ °Q 0 indicates the previous state (the previously stored value)

11 D Latch Q Q’ C D S R X Y X 0 Q 0 Q 0 ’ D C Q Q’ °Input value D is passed to output Q when C is high °Input value D is ignored when C is low

12 Symbols for Latches °SR latch is based on NOR gates °S’R’ latch based on NAND gates °D latch can be based on either. °D latch sometimes called transparent latch

13 Summary of The D Latch °Latches are based on combinational gates (e.g. NAND, NOR) °Latches store data even after data input has been removed °S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) °With additional gates, an S-R latch can be converted to a D latch (D stands for data) °D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q °Next time: more storage elements!

14 Clocking Event Lo-Hi Lo-Hi edge Hi-Lo Hi-Lo edge °What if the output only changed on a C transition? C DQ Q’ X 0 Q 0 Q 0 ’ D C Q Q’ Positive edge triggered

15 Master-Slave D Flip Flop °Consider two latches combined together °Only one C value active at a time °Output changes on falling edge of the clock

16 D Flip-Flop D gets latched to Q on the rising edge of the clock. °Stores a value on the positive edge of C °Input changes at other times have no effect on output C DQ Q’ X 0 Q 0 Q 0 ’ D C Q Q’ Positive edge triggered

17 Clocked D Flip-Flop °Stores a value on the positive edge of C °Input changes at other times have no effect on output

18 Positive and Negative Edge D Flip-Flop °D flops can be triggered on positive or negative edge °Bubble before Clock (C) input indicates negative edge trigger Lo-Hi Lo-Hi edge Hi-Lo Hi-Lo edge

19 Clocked J-K Flip Flop °Two data inputs, J and K °J -> set, K -> reset, if J=K=1 then toggle output Characteristic Table

20 Asynchronous Inputs J, K are synchronous inputs o Effects on the output are synchronized with the CLK input. Asynchronous inputs operate independently of the synchronous inputs and clock o Set the FF to 1/0 states at any time.

21 Asynchronous Inputs

22 Note reset signal (R) for D flip flop If R = 0, the output Q is cleared This event can occur at any time, regardless of the value of the CLK

23 Parallel Data Transfer °Flip flops store outputs from combinational logic °Multiple flops can store a collection of data

24 Designing Finite State Machine °Understanding flip flop state: Stored values inside flip flops °Clocked sequential circuits: Contain flip flops °Representations of state: State equations State table State diagram °Finite state machines Mealy machine Moore machine

25 State Table °Sequence of outputs, inputs, and flip flop states enumerated in state table °Present state indicates current value of flip flops °Next state indicates state after next rising clock edge °Output is output value on current clock edge Present State Next State x=0 x= Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1) x=0 x=1 Output State Table

26 °All possible input combinations enumerated °All possible state combinations enumerated °Separate columns for each output value. °Sometimes easier to designate a symbol for each state. Present State Next State x=0 x=1 s 0 s s 2 s s 0 s s 2 s x=0 x=1 Output s0s1s2s3s0s1s2s3 Let: s 0 = 00 s 1 = 01 s 2 = 10 s 3 = 11

27 Mealy Machine Comb. Logic X(t) Q(t+1) Q(t) Y(t) clk present state present input next state Comb. Logic Output based on state and present input Flip Flops

28 Moore Machine Comb. Logic X(t) Q(t+1) Q(t) Y(t) clk present state present input next state Comb. Logic Output based on state only Flip Flops

29 Mealy versus Moore

30 State Diagram with One Input & One Mealy Output °Mano text focuses on Mealy machines °State transitions are shown as a function of inputs and current outputs. S1 S2 S3 S4 1/0 1/1 Input(s)/Output(s) shown in transition 0/0 e.g. 1 0/0

31 State Diagram with One Input & a Moore Output °Moore machine: outputs only depend on the current state °Outputs cannot change during a clock pulse if the input variables change °Moore Machines usually have more states. °No direct path from inputs to outputs °Can be more reliable

32 Clocked Synchronous State-machine Analysis – next class Given the circuit diagram of a state machine: 1Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input to each flip-flop is based upon current state and circuit inputs. 2Substitute excitation equations into flip-flop characteristic equations, giving transition equations: Q i (t+1) = H i ( D i ) 3From the circuit, find output equations: Z = G (Q, inputs) The outputs are based upon the current state and possibly the inputs. 4Construct a state transition/output table from the transition and output equations: Similar to truth table. Present state on the left side. Outputs and next state for each input value on the right side. Provide meaningful names for the states in state table, if possible. 5Draw the state diagram which is the graphical representation of state table.

33 Concept of the State Machine Computer Hardware = Datapath + Control Registers Combinational Functional Units (e.g., ALU) Busses FSM generating sequences of control signals Instructs datapath what to do next Qualifiers Control Datapath State Control Signal Outputs Qualifiers and Inputs

34 Designing Finite State Machines °Specify the problem with words °(e.g. Design a circuit that detects three consecutive 1 inputs) °Assign binary values to states °Develop a state table °Use K-maps to simplify expressions °Flip flop input equations and output equations °Create appropriate logic diagram °Should include combinational logic and flip flops

35 Example: Detect 3 Consecutive 1 inputs °State S 0 : zero 1s detected °State S 1 : one 1 detected °State S 2 : two 1s detected °State S 3 : three 1s detected 0 °Note that each state has 2 output arrows °Two bits needed to encode state

36 State Table for Sequence Detector °Sequence of outputs, inputs, and flip flop states enumerated in state table °Present state indicates current value of flip flops °Next state indicates state after next rising clock edge °Output is output value on current clock edge Present State Next State A B x A B y Output Input °S 0 = 00 °S 1 = 01 °S 2 = 10 °S 3 = 11

37 Finding Expressions for Next State and Output Value °Create K-map directly from state table (3 columns = 3 K-maps) °Minimize K-maps to find SOP representations °Separate circuit for each next state and output value

38 Circuit for Consecutive 1s Detector °Note location of state flip flops °Output value (y) is function of state °This is a Moore machine.

39 Concept of the State Machine Example: Odd Parity Checker Assert output whenever input bit stream has odd # of 1's State Diagram Symbolic State Transition Table Encoded State Transition Table °Note: Present state and output are the same value ° Moore machine

40 Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS D FF Implementation Timing Behavior: Input

41 Mealy and Moore Machines Solution 1: (Mealy) 0/0 Even Odd 1/1 1/0 0/1 0 Even Reset [0] Odd [1] Output Input Output Input Transition Arc Output is dependent only on current state O/P is dependent on current state and input in Mealy Solution 2: (Moore) Mealy Machine: Output is associated with the state transition - Appears before the state transition is completed (by the next clock pulse). Moore Machine: Output is associated with the state -Appears after the state transition takes place.

42 Vending Machine FSM Step 1. Specify the problem  Deliver package of gum after 15 cents deposited  Single coin slot for dimes, nickels  No change  Design the FSM using combinational logic and flip flops

43 Vending Machine FSM State Diagram Reuse states whenever possible Reuse states whenever possible Symbolic State Table

44 Vending Machine FSM State Encoding How many flip-flops are needed?

45 Vending Machine FSM Determine F/F implementation

46 D Q Q R Q R Q0Q0 N N Q0Q0 Q1Q1 N Q1Q1 D D0D0 D1D1 Q1Q1 OPEN D CLK Vending machine FSM implementation based on D flip-flops(Moore). Q1Q1 Q0Q0 Reset Minimized Implementation

47 Summary °Finite state machines form the basis of many digital systems °Designs often start from clear specifications °Develop state diagram and state table °Optimize using combinational design techniques °Mealy or Moore implementations possible Can model approach using HDL.


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