# Finite State Machines (FSMs)

## Presentation on theme: "Finite State Machines (FSMs)"— Presentation transcript:

Finite State Machines (FSMs)
Today: First Hour: FSM Concept Section 8.1 of Katz’s Textbook In-class Activity #1 Second Hour: Design Example w/ FSM Section 8.2 of Katz’s Textbook In-class Activity #2

A Precursor of Finite State Machines
Counters vs FSMs A Precursor of Finite State Machines • Counters: Simple sequential circuits State = Output No inputs Simple single-path sequencing through the states • Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" or “control” logic

Recap: Synchronous FSMs
Described by State Diagrams, much the same way that combinational logic circuits are described by Boolean Algebra. Current State [output] New State [output] Current Input(s) Change of state happens only on the clocking event

Recap: 3-bit Binary Up-Counter
000 000 001 001 010 010 Each circle corresponds to a state The label inside each circle describes the state 111 111 011 011 Arrows represent state transitions 110 110 101 101 100 100 No labels on arrows, since the counter has no inputs

Example: Odd Parity Checker
Asserts output whenever input bit stream (seen so far) has odd # of 1's Even [0] Odd [1] Reset 1 State Diagram Symbolic State Transition Table Encoded State Transition Table Observe that the output in this case depends only upon the present state, and not upon the input.

Design with Flip-flops
Q Q+ T 0 0 0 0 1 1 1 0 1 1 1 0 Q Q+ D 0 0 0 0 1 1 1 0 0 1 1 1 T F/F: Excitation Table D F/F: Excitation Table D F/F inputs are identical to the next state outputs in the state transition table

Odd Parity Checker Operation
Excitation/Output Functions D = PS  Input; Output = PS D R Q Input Clock PS/Output \Reset D FF Implementation T R Q Input Clock Output \Reset T FF Implementation Timing Behavior: Input Clock Output Input 1

When are inputs sampled, next states computed, outputs asserted?
Timing When are inputs sampled, next states computed, outputs asserted? State Time: Time between clocking events • Clocking event causes state/outputs to transition, based on inputs • For set-up/hold time considerations: Inputs should be stable before clocking event • After propagation delay, Next State entered, Outputs are stable NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event E.g., 3-state enable: effective immediately sync. counter clear: effective at next clock event

Positive Edge Triggered Synchronous System
Timing Example Positive Edge Triggered Synchronous System On rising edge: inputs sampled, outputs & next state computed After propagation delay: outputs and next state are stable Immediate Outputs affect datapath immediately could cause inputs from datapath to change Delayed Outputs take effect on next clock edge propagation delays must exceed hold times Outputs State Time Clock Inputs

Communicating State Machines
One machine's output is another machine's input [0], [1] outputs Could be used to model: bus protocols, handshaking, 2-way communications, etc. Machines advance in lock step Initial inputs/outputs: X = 0, Y = 0

Do Activity #1 Now

Basic Design Approach Six Step Process
1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state minimization 4. Perform state assignment 5. Choose FF types to implement FSM state register 6. Implement the FSM

Vending Machine Concept
General Machine Concept deliver package of gum after 15 cents is deposited single coin slot for dimes, nickels no change

Vending Machine FSM - 1 Step 1. Understand the problem INPUTS OUTPUTS
Block Diagram INPUTS OUTPUTS Draw a picture!

Vending Machine FSM - 2 Step 2. Map into more suitable abstract representation Tabulate typical input sequences three nickels nickel, dime dime, nickel two dimes two nickels, dime Draw state diagram Inputs: N, D, reset Output: open

Vending Machine FSM - 3 Step 3: State Minimization reuse states
whenever possible Symbolic State Table

How many flip-flops are needed?
Vending Machine FSM - 4 Step 4: State Encoding How many flip-flops are needed?

Vending Machine FSM - 5a Step 5. Choose F/Fs for implementation
D F/F easiest to use K-map for Open K-map for D0 K-map for D1 Q1 Q0 D N Q1 Q0 D N

Vending Machine FSM - 5b Step 5. Choose FF for Implementation (continued) J 1 X J-K F/F Remapped encoded state transition table Next State Q0+ X X Present State Q 1 D N Inputs K X J Q1+

Vending Machine FSM - 6a Step 6. Implementation: D F/Fs
D1 = Q1 + D + Q0 N D0 = N Q0 + Q0 N + Q1 N + Q1 D OPEN = Q1 Q0 8 Gates

Vending Machine FSM - 6b Step 6. Implementation: J-K F/Fs
K-map for K1 K-map for J1 Q1 Q0 D N Q1 Q0 D N K-map for K0 K-map for J0 J1 = D + Q0 N K1 = 0 J0 = Q0 N + Q1 D K0 = Q1 N 7 Gates

Do Activity #2 Now For Next Class: Due: End of Class Today.
RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: Sec 8.4 of Katz This reading is necessary for getting points in the Studio Activity!