Presentation on theme: "Finite State Machines (FSMs)"— Presentation transcript:
1Finite State Machines (FSMs) Today:First Hour: FSM ConceptSection 8.1 of Katz’s TextbookIn-class Activity #1Second Hour: Design Example w/ FSMSection 8.2 of Katz’s TextbookIn-class Activity #2
2A Precursor of Finite State Machines Counters vs FSMsA Precursor of Finite State Machines• Counters: Simple sequential circuitsState = OutputNo inputsSimple single-path sequencing through the states• Generalizes to Finite State Machines:Outputs are Function of State (and Inputs)Next States are Functions of State and InputsUsed to implement circuits that control other circuits"Decision Making" or “control” logic
3Recap: Synchronous FSMs Described by State Diagrams, much the same way that combinational logic circuits are described by Boolean Algebra.CurrentState[output]NewState[output]Current Input(s)Change of state happens only on the clocking event
4Recap: 3-bit Binary Up-Counter 000000001001010010Each circle corresponds to a stateThe label inside each circle describes the state111111011011Arrows represent state transitions110110101101100100No labels on arrows, since the counter has no inputs
5Example: Odd Parity Checker Asserts output whenever input bit stream (seen so far) has odd # of 1'sEvenOddReset1StateDiagramSymbolic State Transition TableEncoded State Transition TableObserve that the output in this case depends onlyupon the present state, and not upon the input.
6Design with Flip-flops Q Q+ T0 0 00 1 11 0 11 1 0Q Q+ D0 0 00 1 11 0 01 1 1T F/F: Excitation TableD F/F: Excitation TableD F/F inputs are identical to the nextstate outputs in the state transition table
8When are inputs sampled, next states computed, outputs asserted? TimingWhen are inputs sampled, next states computed, outputs asserted?State Time: Time between clocking events• Clocking event causes state/outputs to transition, based on inputs• For set-up/hold time considerations:Inputs should be stable before clocking event• After propagation delay, Next State entered, Outputs are stableNOTE: Asynchronous signals take effect immediatelySynchronous signals take effect at the next clocking eventE.g., 3-state enable: effective immediatelysync. counter clear: effective at next clock event
9Positive Edge Triggered Synchronous System Timing ExamplePositive Edge Triggered Synchronous SystemOn rising edge: inputs sampled,outputs & next state computedAfter propagation delay: outputs and next state are stableImmediate Outputsaffect datapath immediatelycould cause inputs from datapath to changeDelayed Outputstake effect on next clock edgepropagation delays must exceed hold timesOutputsState TimeClockInputs
10Communicating State Machines One machine's output is another machine's input, outputsCould be used to model:bus protocols, handshaking,2-way communications, etc.Machines advance in lock stepInitial inputs/outputs: X = 0, Y = 0
12Basic Design Approach Six Step Process 1. Understand the statement of the Specification2. Obtain an abstract specification of the FSM3. Perform a state minimization4. Perform state assignment5. Choose FF types to implement FSM state register6. Implement the FSM
13Vending Machine Concept General Machine Conceptdeliver package of gum after 15 cents is depositedsingle coin slot for dimes, nickelsno change
14Vending Machine FSM - 1 Step 1. Understand the problem INPUTS OUTPUTS Block DiagramINPUTS OUTPUTSDraw a picture!
15Vending Machine FSM - 2Step 2. Map into more suitable abstract representationTabulate typical input sequencesthree nickelsnickel, dimedime, nickeltwo dimestwo nickels, dimeDraw state diagramInputs: N, D, resetOutput: open
16Vending Machine FSM - 3 Step 3: State Minimization reuse states whenever possibleSymbolic State Table
17How many flip-flops are needed? Vending Machine FSM - 4Step 4: State EncodingHow many flip-flops are needed?
18Vending Machine FSM - 5a Step 5. Choose F/Fs for implementation D F/F easiest to useK-map for OpenK-map for D0K-map for D1Q1 Q0D NQ1Q0DN
19Vending Machine FSM - 5bStep 5. Choose FF for Implementation (continued)J1XJ-K F/FRemapped encoded state transition tableNext StateQ0+X XPresent StateQ1DNInputsKXJQ1+
20Vending Machine FSM - 6a Step 6. Implementation: D F/Fs D1 = Q1 + D + Q0 ND0 = N Q0 + Q0 N + Q1 N + Q1 DOPEN = Q1 Q08 Gates
21Vending Machine FSM - 6b Step 6. Implementation: J-K F/Fs K-map for K1K-map for J1Q1 Q0D NQ1Q0DNK-map for K0K-map for J0J1 = D + Q0 NK1 = 0J0 = Q0 N + Q1 DK0 = Q1 N7 Gates
22Do Activity #2 Now For Next Class: Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!!For Next Class:Bring Randy Katz Textbook, & TTL Data BookRequired Reading:Sec 8.4 of KatzThis reading is necessary for getting points in the Studio Activity!