1. Dr. ClincyLecture1 Appendix A – Part 2: Logic Circuits Current State or output of the device is affected by the previous states Circuit Flip Flops New Input Previous State or Output Current State or Output Previous State or Output Sequential Logic Circuit New Input Current State or Output Combinatorial or Combinational Logic Current State or output of the device is only affected by the current inputs

2. Dr. ClincyLecture2 Appendix A – Part 2: Logic Circuits Circuit Flip Flops New Input Previous State or Output Current State or Output Previous State or Output Notice how the output feeds the input S and R stand for set and reset respectively constructed from a pair of cross-coupled NOR gates the stored bit is present on the output marked Qa If S and R inputs are both low, maintains the Qa and Qb in constant state, If S (Set) is pulsed high while R is held low, then the Qa output is forced high,and stays high even after S returns low; if R (Reset) is pulsed high while S is held low, then the Qa output is forced low, and stays low even after R returns low.

3. Dr. ClincyLecture3 Gated SR Latch or Flip Flop The time at which the latch is SET or RESET is controlled by a CLOCK input Called Gated SR Latch

4. Dr. ClincyLecture4 Gated SR Latch built using NAND

5. Dr. ClincyLecture5 Gated D Latch Inputs S and R are derived from a single input D Clock pulse controls when the output is triggered Samples the D input at the time the clock is HIGH and stores that info until the next clock pulse

6. Dr. ClincyLecture6 Potential Problem Thus far, the assumption has been the inputs S and R (or D) not changing while CLK is HIGH What would happen if S, R and/or D changed ? The output would change immediately This could be a problem To fix this (next ppt)

7. Dr. ClincyLecture7 DQ Q MasterSlave D Clock Q Q DQ Q Q m Q s D Q m QQ s = D Q Q (a) Circuit (b) Timing diagram (c) Graphical symbol Figure A.28. Master-slave D flip-flop. Clk Master-Slave Flip Flop Use 2 D flip flops – Master – Slave – the Slave’s clock is set to zero – therefore, if there was a change in the Master’s input, D, it wouldn’t effect the slave’s Q value – the slave holds the value Clock’s negative edge causes change The arrow only symbolizes “positive edge” clock - the arrow with the NOT symbolizes “negative edge” clock If D changes while Master CLK is HIGH, Qm changes immediately - Qs stays the same because Slave CLK=0 Once the CLK goes LOW, Slave FF reacts because its CLK=1 – so it thens reflects D

8. Dr. ClincyLecture8 T Flip Flop T Flip Flops are good for counters – changes its state every clock cycle, if the input, T, is 1 Positive-edge triggered flip flop Since the previous state of Q was 0, it complements it to 1

9. Dr. ClincyLecture9 JK Flip Flop Combines the behavior of the SR and T flip flops First three entries are the same behavior as the SR Latch (when CLK=1) Usually the state S=R=1 undefined – for the JK Flip Flop, for J=K=1, next state is the complement of the present state Can store data like a D Flip Flop or can tie J & K inputs together and use to build counters (like a T flip flop)

10. Dr. ClincyLecture10 DQ Q Figure A.33. A simple shift register. Clock DQ Q DQ Q DQ Q InOut F 1 F 2 F 3 F 4 Registers and Shift Registers A Flip Flop can store ONE bit – in being able to handle a WORD, you will need a number of flip flops (32, 64, etc) arranged in a common structure called a REGISTER. All flip flops are synchronized by a common clock Data written into (loaded) flip flops at the same time Data is read from all flip flops at the same time Want the ability to rotate and shift the data Clock pulse will cause the contents of F1, F2, F3 and F4 to shift right (serially) To do a rotation, simply connect OUT to IN

11. Dr. ClincyLecture11 Registers and Shift Registers Can load either serially or in parallel When clock pulse occurs, Serial shift takes place if Shift’/Load=0 or if Shift’/Load=1, parallel load is performed

12. Dr. ClincyLecture12 Counters 3-stage or 3-bit counter constructed using T Flip Flops With T Flip Flips, when input T=1, the flip flop toggles – changes state for each successive clock pulse Initially all set to 0 When clock pulse, Q0=1, therefore Q’=0 disabling Q1 and Q1 disables Q2 (have 1,0,0) For the 2 nd clock pulse, Q0=0, therefore Q’=1, causing Q1=1 and therefore Q’=0 disabling Q2 (have 0,1,0) For the 3 rd clock pulse, Q0=1, therefore Q’=0 disabling Q2 and therefore disabling Q3 (have 1,1,0) Etc…. 000 001 010 011 100 101 110 111 Hmmm LSB Called a Ripple Counter

13. Dr. ClincyLecture13 Decoders Input - Encoded message Output - Decoded message Example – encoded message 01 means 2

14. Dr. ClincyLecture14 Decoders – another example

15. Dr. ClincyLecture15 Multiplexers Depending the “select input” combination, 1 of 4 data inputs is chosen for output Example – if “select input” 10 is realized, data input on X 3 is displayed as output, Z Explain how you rotate here to get different info coming out the mux

16. Dr. ClincyLecture16 Multiplexers Can also use multiplexers to implement logic functions Given this truth table, group X1,X2 being 00, 01, 10 and 11 – notice what happens with X3 3-input truth table can be done with a 4-input mux 4-input truth table can be done with a 8-input mux 5-input truth table can be done with a 16-input mux Etc..