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1 Sequential logic networks State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input V. Sequential network.

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Presentation on theme: "1 Sequential logic networks State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input V. Sequential network."— Presentation transcript:

1 1 Sequential logic networks State-machine structure (Mealy) typically edge-triggered D flip-flops output depends on state and input V. Sequential network design

2 2 Sequential logic networks State-machine structure (Moore) output depends on state only typically edge-triggered D flip-flops V. Sequential network design

3 3 Sequential logic networks Q Q’C D Q C S R Q C J K Characteristic Table S R q Q J K q Q D q Q Characteristic Equation Q = D SR q d d1 1 Q = S + R’q JK q Q = Jq’ + K’q Transition Table (Excitation Table) q  Q D 0  0 0  1 1  0 1  q  Q S R 0  0 0  1 1  0 1  1 0 d d 0 q  Q J K 0  0 0  1 1  0 1  1 0 d 1 d d 1 d 0 D Flip flopS-R Flip flopJ-K Flip flop q : Current state Q : Next state V. Sequential network design Flip Flop : summary

4 4 Sequential logic networks Characteristic table : For each input and state combination, define the next state of the flip flop Characteristic equation: Define the next state (Q) as a function of current state and input to the flip flop Transition table (excitation table): For each transition type, define the inputs that cause the transition V. Sequential network design Flip Flop : summary

5 5 Sequential logic networks Step 1: Start from state diagram or word description Step 2: Construct a State/Output table Moore machine: one output per state (one output column) Mealy machine: One output per state and for each input combination (one output column per input combination) Step 3: Reduce the number of states in State/output table by removing redundant states (a state is redundant if for the same input combinations) it has the same next state and output as another state. Step4: Encode the states in binary (for n states, log 2 n bits are required). Each bit in the code represents a flip flop. Step5: Substitute corresponding binary codes to states in the State/Output table Step6: Separate the state table into flip flop next state maps (one map for each bit or flip flop) Step7: Use the flip flop next state map to derive flip flop excitation maps (this step depends on the type of flip flop used in the design) Step8: Use the flip flop excitation maps to determine excitation equations for the flip flop (these equations define the input logic of the flip flop) Step 9: Use the State/Output table to define the output logic circuit Step10: Draw the circuit, including flip flop, flip flop input circuits and output circuit. V. Sequential network design Major design steps

6 6 Sequential logic networks Example 1 Step1: Problem Description (Word description) Design a sequential machine that detects a 01 sequence. The detection of sequence sets the output, Z=1, which is reset (Z=0) only by a 00 input sequence Note: The input is scan one bit at a time V. Sequential Network Design

7 7 Sequential logic networks Example 1: STEP 1 Step1: State Transition Diagram of the sequential machine: Recall that a State Transition Diagram consists of :  States (representated by circles)  Transitions (represented as arcs) between states  Transitions are labelled by input that cause them  Output are associated with –input labels (MEALY MACHINE) –State labels (MOORE MACHINE) V. Sequential Network Design

8 8 Sequential logic networks Example 1: STEP1 V. Sequential Network Design State diagram of example 1 (Mealy Machine): 0/0 1/1 0/1 1/0 A State Description: A : initial state (sequence does not begin) B 0/0 B : 0 is detected, expecting a 1 C 1/1 C : 01 sequence detected, output set to 1 Must detect a 00 to reset output to 0 First 0 detected, go to B to wait for second 0

9 9 Sequential logic networks Example 1: STEP 2 V. Sequential Network Design For each (current state, input) pair, specify: Next State Output State/Output table (Mealy Machine) CS X=0 A B A B B C C B C X= 1X=0X= NS Output 0/0 1/1 1/0 A B 0/0 C 1/1 0/1 State/Output table

10 10 Sequential logic networks Example 1: STEP2 V. Sequential Network Design State diagram (Moore Machine): A,0B,0 0 C,1 1 D, A: Waiting for start of sequence 01 and output 0 B: 0 is detected, wait for 1 and output 0 C: Sequence 01 is detected, output 1 and wait for 00 to reset output D: Start of 00 is detected; wait for the final 0 to reset output when we get 0, go to B and output 0 When we get 1, go back to C to wait for 00 sequence

11 11 Sequential logic networks Example 1: STEP 2 V. Sequential Network Design State /Output Table: CS NS X=0X= 1 A B A B B C C D C Output A,0B,0 0 C,1 1 D, D B C 1

12 12 Sequential logic networks Example 1: STEP 3 V. Sequential Network Design State /Output Table: CS NS X=0X= 1 A B A B B C C D C Output D B C 1 Reduce the number of states in STATE/OUTPUT table: NO Redundant states in example 1 Output does not Depend on input X

13 13 Sequential logic networks Example 1: STEP 4 V. Sequential Network Design State Assignment: Encode the different states There are 3 states  We need two States Variable y1 and y0 y1 is the leftmost bit (Flip flop 1) y0 is the rightmost bit (Flip flop 0) One possible state assignment: A  00, B  01, C  10 : State code 11 is not used (don’t cares …) There are many more state assignments: For example, We could use the following assignments A  11, B  10, C  01 : State code 00 is not used (don’t cares …) A  10, B  11, C  00 : State code 01 is not used (don’t cares …)

14 14 Sequential logic networks Example 1: STEP 5 V. Sequential Network Design Substitute State Codes in the State/output table State assignment: A  00, B  01, C  10 State/Output table (Mealy Machine) CS NS X=0X= Output X=0X= dd dd d d CS NS X=0X= 1 A B A B B C C B C Output X=0X= Unused state code

15 15 Sequential logic networks Example 1: STEP 6 V. Sequential Network Design Flip Flop Next State Maps State/Output table (Mealy Machine) CS NS X=0X= Output X=0X= d d d d d d (y1y0) X d d CurrentNext state Y1 Flip flop 1 (y1y0) X d d CurrentNext state Y0 Flip flop 0 Flip flop Next state maps y1 (flip flop 1)y0 (flip flop 0)

16 16 Sequential logic networks Example 1: STEP 7 V. Sequential Network Design Flip Flop Excitation Maps Determine transitions of flip flop For each transition, give the input that cause the transition (Depends on the type of flip flops) Assume JK flip flop for y1 and y0 (y1y0) X d d CurrentNext state Y1 Flip flop 1 (J1, K1) Next transition for X=0 and X= d 0 d d 1 d 1 0 d 1 d d d d d (y1y0) X 0 1 CurrentNext state Y1 Flip flop 1 (J1, K1) J1 K1

17 17 Sequential logic networks Example 1: STEP 7 V. Sequential Network Design Flip Flop Excitation Maps Assume JK flip flop for y1 and y0 Next transition for X=0 and X= d 0 d 0 1 d 0 d d 0 d 1 1 d d d d (y1y0) X 0 1 CurrentNext state Y0 Flip flop 0 (J0, K0) J0 K0 (y1y0) X d d CurrentNext state Y0 Flip flop 0

18 18 Sequential logic networks Example 1: STEP 8 V. Sequential Network Design Flip Flop Excitation Equations (Input circuits of flip flops) Derive K- Maps from excitation maps Use K-maps to derive flip flop input equations (y1y0) X d 0 d d 1 d 1 0 d 1 d d d d d CurrentNext state Y1 Flip flop 1 (J1, K1) J1 K1 K1 input J1 input y1y0 X J1 0 0 d d 0 1 d d J1 = xy0 y1y0 X K1 d d d 1 d d d 0 K1 = x’

19 19 Sequential logic networks Example 1: STEP 8 V. Sequential Network Design Flip Flop Excitation Equations (Input circuits of flip flops) Derive K- Maps from excitation maps Use K-maps to derive flip flop input equations y1y0 X K0 d 0 d d d 1 d d K0 = X y1y0 X J0 1 d d 1 0 d d 0 J0 = X’ (y1y0) X d 0 d 0 1 d 0 d d 0 d 1 1 d d d d CurrentNext state Y0 Flip flop 0 (J0, K0) J0 K0 J0 input K0 input

20 20 Sequential logic networks Example 1: STEP 9 V. Sequential Network Design Determine the output logic circuit State/Output table (Mealy Machine) y1y0 NS X=0X= Output Z X=0X= dd dd d d y1y0 X Z 0 0 d d 1 Z = y1 + xy0 K-map of output Z

21 21 Sequential logic networks Example 1: STEP 10 V. Sequential Network Design Draw the circuit: (Flip flops and logic gates) X CLK y1 J1Q K1 y0 J0 Q K0 Input circuit Memory components Output circuit OR Z

22 22 Sequential logic networks Homework V. Sequential Network Design Design the 01 sequence detector as a Moore machine. The ouput is reset 0 when a 00 sequence is detected. Design the detectector using: clocked JK flip flops clocked D flip flops

23 23 Sequential logic networks Example 2 V. Sequential Network Design Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping. For example, for the input sequence X = , the corresponding output Z is Z = State diagram (Moore Machine): 0 A,0B,0C,0D,0 1 0 E, Overlapping

24 24 Sequential logic networks Example 3 V. Sequential Network Design Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string. Design the detectector using: clocked JK flip flops clocked D flip flops

25 25 Sequential logic networks Example 4 V. Sequential Network Design Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi-bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit. Assume two outputs Z1Z2 such that: Z1 = 1 if X > Y Z2 = 1 if X < Y Z1= Z2 = 0 if X = Y

26 26 Sequential logic networks Example 5 V. Sequential Network Design Design a two-bit clocked sequential counter circuit that counts clock pulses.

27 27 Sequential logic networks Design examples Example1 Give the state diagram of a clocked sequential circuit that recognizes the input sequence 1010, including overlapping. For example, for the input sequence X = , the corresponding output Z is Z = Example2 Design a Moore synchronous sequential circuit to detect a string of of three or more consecutive 1’s in an arbitrary input string. Design the detectector using: clocked JK flip flops clocked D flip flops Example3 Using D flip flops, design a Moore synchronous sequential comparator circuit to determine which of the two multi- bits binary numbers X and Y (of equal Length) is larger. The comparison is carried out from left (Most Significant Bit) to right. Both MSB are used as input to the circuit. Assume two outputs Z1Z2 such that: Z1 = 1 if X > Y Z2 = 1 if X < Y Z1= Z2 = 0 if X = Y Example4 Design a two-bit clocked sequential counter circuit that counts clock pulses.


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