Download presentation

Presentation is loading. Please wait.

Published byRodrigo Waithe Modified over 3 years ago

1
Sequential Logic Computer Organization Ellen Walker Hiram College Figures from Computer Organization and Design 3ed, D.A. Patterson & J.L. Hennessey, Morgan Kauffman © 2005 unless otherwise specified

2
Sequential Logic Combinational logic “forgets” its results when the inputs are no longer available Sequential logic “remembers” results until the next clock signal

3
A Memory Cell ~Q = 0 (or 1) Q = 1 (or 0)

4
A Settable Cell Replace NOT with NOR 0 NOR Q = ~Q –As before 1 NOR Q = 0 –Set / reset cell

5
Truth Table for SR Latch RSQ~Q 00Q’~Q’ 0110 1001 11??

6
Clock Signal Periodic alternation between 0 and 1 Does not have to be evenly divided Example: One period Rising edgeFalling edge

7
Clocked D Latch CDQ~Q 00Q’~Q’ 01Q’~Q’ 1001 1110

8
Action of D Latch D C Q

9
Latch vs. Flip Flop Latch changes by level –As long as C is high, Q follows D Flip flop changes by edge –Q takes value of D at rising (or falling) edge only

10
D Flip-Flop with Falling Edge Trigger When C is high, “master” follows D When C is low, “slave” follows Q of “master” When C is low, Q of “master” is locked in.

11
Action of D Flipflop D C Q

12
Setup and Hold Time Setup time: Minimum time D must be stable before clock edge Hold time: Minimum time D must be stable after clock edge

13
Determining Clock Cycle Combinational logic must be done before D needs to be stable Therefore, (combinational logic + setup time + hold time) < clock cycle

14
Other Flip Flops T (toggle): When T is set, flip-flop changes value at clock edge JK (very general ff) –When J=K=1, toggles at edge –When J=1, K=0, sets at edge –When J=0, K=1, resets at edge –When J=K=0, holds value

15
Counter from T Flip Flops Low Order Bit: –T=1, clock = external signal Each additional bit: –T=1, clock = Q from lower bit –When lower bit falls, higher bit toggles Delay increases as # bits increase (“ripple effect”)

16
Sequential Circuit Allows Feedback Combinational Logic D C Q External inputs Clock signal

17
Register from D Flip Flops One register is simply a set of D flip- flops, one per bit Data inputs are D’s Data outputs are Q’s and ~Q’s Clocks all tied together

18
Register File Several registers grouped together To read: –Input = register # –Output = register data To write: –Inputs = register #, register data, clock (write signal) –Output = (none)

19
Implementing Read Ports

20
Implementing Write Ports

21
4x2 DRAM from D-FFs

22
State Machine Sequential logic holds state Combinational logic computes new state and output (based on old state)

23
Graphical Representation

24
Building a State Machine Determine the states and transitions Assign numbers to the states –If there are N states, you need log N flip flops to hold the state number Create “next state” logic Create “output” logic

25
Example: Parity Checker One input, which sequentially gets the bits of a word One output, 0 if number of 1’s since reset is even, 1 if number of 1’s since reset is odd Asynchronous reset sets parity back to 0

26
Pattern Recognizer Input: Sequence of Bits Output: –If last 2 bits were “10” output is 1 –If bit pattern “111” is found, output is 0 and remains 0 no matter what –Otherwise, output is 0

Similar presentations

Presentation is loading. Please wait....

OK

© 2018 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on resistance temperature detector manufacturers Viewer ppt online Ppt on javascript events status Sample ppt on personality test Ppt on generation of electricity from wastewater Ppt on pin photodiode Ppt on different types of forests in the united Ppt on job evaluation point Ppt on dry drunk syndrome Ppt on road accidents in kenya