MICAS Department of Electrical Engineering (ESAT) Logic style 1. Standard CMOS logic 2. Pseudo NMOS logic 3. MCML (MOS Current Mode Logic--differential.

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MICAS Department of Electrical Engineering (ESAT) Logic style 1. Standard CMOS logic 2. Pseudo NMOS logic 3. MCML (MOS Current Mode Logic--differential version of CSL) 4. CSL (CMOS Current Steering Logic) AID–EMC: Low emission Digital Circuit Design

MICAS Department of Electrical Engineering (ESAT) Why CSL ? Target : Mixed-Mode Automotive Electronics Design Key aspect : di/dt + Power + Area + Speed Current Steering Logic

MICAS Department of Electrical Engineering (ESAT) CSL – Static Characteristic Design Parameter: R= Vdd=2.5v I=20uA

MICAS Department of Electrical Engineering (ESAT) CSL – Noise Margin Vdd=2.5v I=20uA

MICAS Department of Electrical Engineering (ESAT) CSL – Dynamic Characteristic Vdd=2.5v I=20uA

MICAS Department of Electrical Engineering (ESAT) Vdd=3.3v I=10uA R=6 Cd The Effect of Decoupling Capacitance 1p 10p,100p,1n,10n There is a Trade off !

MICAS Department of Electrical Engineering (ESAT) Comparison of 16-bit RCA Note: Vdd=1.5v The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. Solution: power consumption management power down strategies, sleeping transistors, … Power vs. Frequency (16-bit RCA) 0.00E E E E E E E E E E Frequency(Mhz) Power(Watt) CMOS CSL

MICAS Department of Electrical Engineering (ESAT) Spectrum Analysis of di/dt Power Spectral Analysis of the CMOS 16-bit RCA Frequency (Hz) Power GABARIT ? 30db decrease