1. Low Power – High Speed MCML Circuits (II)
Shahnam Khabiri
95.575
March, 2002

2. Outline: Introduction CSL and MCML operation
CMOS, MCML, CML, ECL comparison
DyCML
Feedback MCML
Adaptive pipeline system for MCML
Conclusion
References

3. Introduction VLSI development goals: - Large integration density
High speed operation
Low power dissipation
Low cost

4. Introduction … Why CMOS: Why not CMOS: - High packing densities
High noise margin
Simplicity
No static power dissipation
Yield
Low cost, …
Switching noise in mixed mode ASIC’s
f   P 
Vdd   P , but Delay  , …

5. Current Steering Logic (CSL)
Advantage:
Reduced power supply current noise
Disadvantage:
Additional output branch for each fanout
Static power dissipation
Frequency proportional dynamic power dissipation

6. MCML Operation Rise time depends on RL (RFP voltage)
Fall time depends on I (RFN voltage)
NMOS current source has longer L to provide high ro
Less sensitivity to noise margin and gain, therefore :
gain could be set to 1.4
and Vswing set to 300mv

7. MCML Logic Gates

8. CMOS, MCML, CML, ECL CMOS MCML CML ECL Delay C.Vdd/[K(Vdd-VT)2] C.V/I
CMOS
MCML
CML
ECL
Delay
C.Vdd/[K(Vdd-VT)2]
C.V/I
<Tcml
Power
C(Vdd)2.f
Vdd.I
>Pcml
Vms
VT = 0.6 v
(I/K)0.5+VT = 0.9 v
2VBE+VSC = 1.8 v
3VBE+VSC = 2.6 v

9. CMOS, MCML, CML, ECL …

10. Simulated results for an MCML F.A.
MCML Full Adder in 0.5um
Vdd = 1.2 v
delay = 200ps
CMOS:
Vdd = 3.3 v, delay = 600ps
Vdd = 1.5 v, delay = 2ns

11. Experimental results for an MCML F.F
0.5 um cmos, f = 1.8 GHz
Delay between clock edge and output = 160ps

12. DyCML Advantage: Vswing.CL = WC1.LC1.Cox.(Vdd-Vswing) C1 size
Dynamic current source
No static power dissipation
More stability in compare with other dynamic circuits
Supply voltage is as low as Vtn+|Vtp|

13. DyCML … Cascading: 1- Clock Delay mechanism (CD) less stability
2- Self Timing scheme (ST)
higher delay and power consumption

14. Simulation results for DyCML
Using 0.6 um CMOS
Vdd = 3.3 v, f = 100MHz
DyCML more suitable for complex gates
ST is slower than CD and consumes more power

15. Feedback MCML Effect of Vth fluctuation: Vth fluctuation is due to:
Fluctuation of gate oxide thickness
Fluctuation of gate length
Random placement of the channel dopant
VB = G(0).Vth
G(0)  VB

16. Feedback MCML … If GC(fmax) = GF(fmax)  GF(0) < GC(0) 
VB is smaller 
More tolerance for several GHz
- LMF1 and LMF2 are larger than minimum

17. Feedback MCML 1:2 Demux and simulation results:
Feedback MCML tolerates two times more Vth fluctuation in compare with conventional MCML
Experimental results show 10 Gb/s Mux, Demux 1:8 in 0.18um use ¼ power of GaAs or Si bipolar and faster than CMOS.
Feedback MCML Latch implementation

18. MCML Optimization in Mixed Signal Applications …
Voltage Swing Control (VSC):
VSC allows fixed voltage swing across variety of currents and easy trade off speed for power
Drawbacks:
Power and area overhead
different gates won’t track Vlow exactly so hard to share VSC

19. Adaptive pipeline system for MCML
Current Source Controller:
RFN and consequently I will be set based on critical path delay requirements
Circuit timing insensitive to process, temperature and voltage variation.
Design for nominal delay and not the worst case delay

20. Full Adder in MCML We can use Current scaling to increase Carry speed
For small number of bits <16 bits CLA is not a great help

21. Experimental Results:
Using 0.25 CMOS process for a 12 bits CORDIC Full Adder
Power results of MCML are up to 1.5 times less than CMOS CORDIC’s with similar propagation

22. Conclusion MCML advantages: High speed:
Tcmos > Tmcml > Tcml > Tecl
NMOS devices, Low voltage swing, All ON Transistors
Low power consumption
@500MHz with applicable Vdd’s:
Pcmos > Pecl > Pcml > Pmcml
Flexible to construct any logic circuit
High speed compact circuits are feasible
P is constant with increasing f (good for high speed applications)
Fixed power supply current (good for mixed signal ASIC’s)
Vdd  P , No effect on Delay

23. Conclusion … MCML advantages: Small Vswing reduces cross talk
Common noise rejection capability
MOS related advantages:
good yield, small area, low cost, low supply voltage
No theoretical minimum for E.D
For a linear chain of N identical MCML gates:
E.D = N3.C2.Vdd.V2/I
I  E.D
Flexibility in design optimization:
Vswing, I, Vdd, Transistor sizes

24. Conclusion … MCML disadvantages:
VT deviation impact on functionality and delay
Static power
Not suitable for power down mode systems
Large load resistors need large area
Matching of rise and fall delays
Shallow depth logic is a limit for MCML

25. References:
Yamashina, Yamada,”An MOS Current Mode Logic Circuit for Low Power GHz Processors”, NEC Res & Dev, 1995.
J.Rabaey, J.M.Musicer,”MOS current mode logic for low power, low noise CORDIC computation in mixed signal environment”, 2000.
A.Tanabe,”0.18 u CMOS 10 Gb/s Multiplexer/Demultiplexer Ics using current mode logic with tolerance to Threshold Voltage fluctuation”,IEEE J. Solid State Circuits, Vol36, No 6, June 2001.
M.W.Allam, M.I.Elmasry,”Dynamic current mode logic: a new low power high performance logic style”,IEEE J. Solid State Circuits, Vol36, No 3, March 2001.
D.J.Allostot,”Current mode logic techniques for CMOS mixed-mode ASIC’s”,IEEE Custom Integrated Circuits Conf., 1991.