1. MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit October 27th, 2005 AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

2. MICAS Department of Electrical Engineering (ESAT) Outline 1. Introduction 2. Logic family selection 3. Clock strategy selection (not discuss today due to lack of time) 1. clock skew 2. SSCG 3. Delay cell array approach 4. Low noise power supply – EMI reducer 1. continuous time 2. stability analysis 3. future work

3. MICAS Department of Electrical Engineering (ESAT) Part I: Introduction Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit, Most of them are due to power and ground fluctuation. Although the detailed calculation of EMI noise is rather difficult, we can use the di/dt as the index, since the current loop contributes the EMI.

4. MICAS Department of Electrical Engineering (ESAT) Part 2: Logic Family Selection SCMOS PNMOSRSBCMOS CSL MCMLFSCL

5. MICAS Department of Electrical Engineering (ESAT) Comparison of di/dt,power and area Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages (Static + Dynamic) Current Steering Logic But there is static power !!

6. MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS Note: The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. CSL One-bit Adder IT is a static power problem, Switching off when standby ?

7. MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS SCMOS CSL SCMOS CSL

8. MICAS Department of Electrical Engineering (ESAT) Problem with CSL Mismatch sensitive, annoying for standard cells rather slow/power hungry Not full swing Matching required! M1 > M3

9. MICAS Department of Electrical Engineering (ESAT) Can we do it better ? C-CBL: sizing for optimal current balance is really difficult,process dependent CBL [Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]

10. MICAS Department of Electrical Engineering (ESAT) Solution- Enhanced current steering logic Still current source basing Increase in logic level, hence increase the robustness Reduced output capacitance, hence the speed is increased Fig.3 E-CSL inverter Minimum size

11. MICAS Department of Electrical Engineering (ESAT) Comparison of CSL, C-CBL, ECSL and SCMOS Fig.5 di/dt vs. frequencyFig.4 power vs. frequency Ring Oscillator of 21-stages

12. MICAS Department of Electrical Engineering (ESAT) di/dt performance vs. process variation Fig.6 di/dt vs. process corner MAX di/dt change MIN di/dt change Ring Oscillator of 21-stages

13. MICAS Department of Electrical Engineering (ESAT) Conclusion of Low noise Logic Families Winner is E-CSL CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique. Current source ensures the major di/dt reduction, Process variation sensitivity also becomes better due to the dominance of current source, E-CSL gives comparable di/dt performance with CSL, E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance. Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large digital systems. Can be solved by using power down strategies, which is highly application dependent

14. MICAS Department of Electrical Engineering (ESAT) Part 4: Low Noise Power Supply design However 2 problems still remain: Static power consumption New logic family standard cell library must be designed and characterised. (large NRE cost, risk) ?? Is there any global approach ??

15. MICAS Department of Electrical Engineering (ESAT) Principles of Low Noise Power supply Fig.9 Diagram of Low noise power supply 1.Current source ensures the major di/dt reduction 2. Do not give more current than the circuit needs, i.e. minimize the static current 3. Slow varying is key to EMC success 1.Can be done with switched or continuous mode. Both are studied, 2. Continuous mode potentially has better di/dt suppression.

16. MICAS Department of Electrical Engineering (ESAT) Continuous mode Power Delivery Fig.13 Continuous time power delivery system Determine the switching speed, Hence determine the di/dt Energy reservoir when slow Switching

17. MICAS Department of Electrical Engineering (ESAT) Functionality Simulation Fig.14 Functionality simulation of continuous time power delivery system continuous time OTA feedback loop stable Idd di/dt Vcontrol VDD_input 9v9v 2 nd order under damped behaviour, still under study VDD_input Vcontrol

18. MICAS Department of Electrical Engineering (ESAT) Comparison with standard CMOS Fig.15 di/dt and FFT comparison with standard CMOS w/o CT, 3.3V only 12v supply current 12v supply current di/dt p-p = 1.0x10 7 A/s di/dt w/o CT, di/dt p-p =1.51x10 11 A/s 162 times= 44dB

19. MICAS Department of Electrical Engineering (ESAT) Stability analysis - Small signal analysis dominant pole second-dominant pole high frequency poles mirror factor p1 p2 p4 p3 >3 for > 72° phase margin (2 nd order system) Approximation:

20. MICAS Department of Electrical Engineering (ESAT) Stability analysis- Calculation vs. Simulation Maple Spectre --------------------------------------------------------------- DC gain(dB): 97.72 97.25 --------------------------------------------------------------- Phase Margin(degree): 62.5 49 --------------------------------------------------------------- Gain Crossover(Hz): 325K 275K ---------------------------------------------------------------- P2/GBW: 1.275 1.264 ---------------------------------------------------------------- (dB) (deg)

21. MICAS Department of Electrical Engineering (ESAT) Trade-off in Ctank and Caux P2/GBW 3 3 Ctank=100pF Caux=100pF

22. MICAS Department of Electrical Engineering (ESAT) Current pulse step response An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation Can be improved if more stable ~10 4 reduction !!

23. MICAS Department of Electrical Engineering (ESAT) Coupling problem ! Cgs 1,2 ≈ Cgd1 ∆ V DD_input ∆ V bias

24. MICAS Department of Electrical Engineering (ESAT) Future work Improve circuit structure to reduce coupling between output node and gate of the current source transistor Figure out supply current behaviour of a typical AMIS digital block Add a real voltage regulator into consideration

25. MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention