1. MICAS Department of Electrical Engineering (ESAT) AID–EMC: Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene Update of the “Digital EMC project” June 2rd, 2005

2. MICAS Department of Electrical Engineering (ESAT) Problem with CSL Mismatch sensitive, annoying for standard cells rather slow/power hungry Not full swing Matching required! work on large block (8051) delayed

3. MICAS Department of Electrical Engineering (ESAT) Another Low-Noise Logic Family----CBL Current Balanced Logic - CBL Fig.1 CBL-generic gateFig.2 CBL-inverter

4. MICAS Department of Electrical Engineering (ESAT) How does CBL work ? Fig.3 CBL-inverter Fig.4 Current balancing [1]

5. MICAS Department of Electrical Engineering (ESAT) Advantage of CBL Fig.5 CSL-inverterFig.6 CBL-inverter Almost rail-rail output voltage swing Small device size for the same supply (I DD, V DD ) Faster due to the lower area and lower capacitance

6. MICAS Department of Electrical Engineering (ESAT) Advantage of CBL - continue Noise Margin Comparison [2] Simulation environment: 1.VDD= 2 V 2.TSMC 0.25um 3.V OH > 1.5 V (CSL) Fig.7 NM of CMOS Fig.8 NM of CSL Fig.9 NM of CBL CBL is more robust while having better noise properties than csl

7. MICAS Department of Electrical Engineering (ESAT) Disadvantage of CBL CBL in Submicron Technology [3] Fig.10 Normalized supply current of the submicron CBL inverter Simulation environment: 1.VDD= 2 V 2.TSMC 0.25um Note: Constant current can not be completely balanced velocity saturation degrades “slope matching”

8. MICAS Department of Electrical Engineering (ESAT) Disadvantage of CBL - continue Fig.12 CBL-inverter No Power down technique available current can still flow here

9. MICAS Department of Electrical Engineering (ESAT) Proposed CBL variant Fig.13 Proposed CBL variance Transistor Mp2: 1.Support the power down mode 2.Size to balance the supply current I DD

10. MICAS Department of Electrical Engineering (ESAT) CBL variant - Speed vs. I DD Fig.14 Simulated Speed vs. I DD of CBL variance Simulation condition: 1.VDD= 3 V 2.AMIS 0.35um

11. MICAS Department of Electrical Engineering (ESAT) Comparison of CBL variant and CSL Fig.14 Simulated waveform of 21-stage ring oscillator- Output voltage 42.336 ns 124.11 ns CBL variance CSL Simulation condition: 1.VDD= 3 V 2.C Load= 5 fF 3.AMIS 0.35um 4.I DD = 3 uA Tp: 1.008 ns 2.995 ns V OH : 3 v 1.51 v V OL : 0.012 v 0.0147 v Area: 2.08 um 2 7.2 um 2 CBL variantCSL

12. MICAS Department of Electrical Engineering (ESAT) Comparison of Noise performance CBL variance CSL CSL: ΔI DD =2.1 uA I DD-nominal =63uA CBL variance: ΔI DD = 3 uA I DD-nominal =63uA Fig.15 Simulated waveform of 21-stage ring oscillator- Supply current I DD Supply current I DD

13. MICAS Department of Electrical Engineering (ESAT) Comparison of Noise performance - continue Fig.16 Simulated waveform of 21-stage ring oscillator- di/dt of supply current I DD CSL: di/dt p-p =2.5K A/s CBL variant: di/dt p-p =17K A/s di/dt of supply current Reference Standard CMOS 150 kA/s

14. MICAS Department of Electrical Engineering (ESAT) Problem: Effect of process variations 2 3 2.5 4 CSL max di/dt [kA/s_pp] 10SS 60SF 12FS 70FF 17TT CBL max [kA/s_pp] Process This is still under investigation. Caused by the fact that sizing for optimal current balance is deteriorated by process variations. Less problematic in CSL due to dominance of current source

15. MICAS Department of Electrical Engineering (ESAT) other idea under investigation Still rely on current balancing Apply current balancing per block and not per gate Questions  is this feasible?  power versus performance?  size of the blocks to be compensated?

16. MICAS Department of Electrical Engineering (ESAT) Conclusion Comparison of CSL vs CBL ongoing. CBL seems more acceptable but problem with sensitivity of di/dt to process parameters Global compensation? CSL is feasible  but standard cell strategy will be more difficult due to matching and robustness issues.  will be more power hungry

17. MICAS Department of Electrical Engineering (ESAT) References 1. A new low-noise logic family for mixed-signal integrated circuits Albuquerque, E.; Silva, M.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 46, Issue 12, Dec. 1999 Page(s):1498 - 1500 2. Static series-voltage noise margins of CBL, CSL and CMOS Szabo, A.; Butkovic, Z.; Electronics, Circuits and Systems, 2002. 9th International Conference on Volume 2, 15-18 Sept. 2002 Page(s):587 - 590 vol.2 3. A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits Albuquerque, E.F.M.; Silva, M.M.; Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on Volume 52, Issue 4, April 2005 Page(s):734 - 741