Digital Logic Design Lecture # 15 University of Tehran

Outline More on the Programmable Devices More on the Transistor Structure Computer Aided Design

More on the Programmable Devices Going back to our discussion of programmable devices remember the memory form mentioned as in the figures below:

More on the Programmable Devices (continued…) Consider the problem where we need to store 8 bit words then we need to cascade such 4 bit packages horizontally like:

More on the Programmable Devices (continued…) Let’s consider another problem where cascading is needed: Build a 32 * 4 ROM using 4 8 * 4 ROMs. As can be seen from the problem description we need 5 addresses lines. In order to expand our address lines vertical cascading is needed, as you can see in the following figure, based on what A 4 and A 3 are, one of the four packages works. This can be done by using a 2-to-4 decoder. Pay attention to the figure shown in the next slide.

More on the Programmable Devices (continued…)

Let us now recalling the feedback procedure used in PAL packages when we had a lack of product terms for a function. When adding a feedback we must note that we are adding a level of logic and thus adding delays.

More on the Programmable Devices (continued…) Consider a problem where we need 12 inputs and 4 output lines to be realized with an 8 input, 8 I/O PAL package. In this case, 4 of the I/O lines can be used as inputs. The structure of the I/O lines is shown in the following figure:

More on the Programmable Devices (continued…) This can be seen better if we look at a standard PAL block. Observe the following figure of a PAL16L8 (16 I/Os, 8 blocks):

More on the Programmable Devices (continued…) In the one block of the last PAL that has been completely drawn, 2 things must be noted. The first is the manner of feedback which we just explained and the second that manner in which the invert of an input has been issued. Here we have not used the below structure: Because there would be no buffering done on one line and fan out problems may occur. Instead we have used the following structure:

More on the Programmable Devices (continued…) The use of three state buffers on the I/Os of the device is mainly for two reasons: One is that when using them an I/O can be either used as an input or output as issued by its control signal (which has to come from an input to the device). The second reason is to do with driving busses. When we want to use a package in a three state bussing structure, we need to have three state outputs so that the outputs and the bus can be simply wired together without the need for extra hardware as glue logic.

More on the Programmable Devices (continued…) ROM packages also have the above structure, which is useful when using them with busses. Note: EEPROM packages can unlike EPROM packages be programmed on board and after we have entered them onto our design board, whereas EPROMs have to be programmed beforehand and don’t have such a capability. PAL packages are also called Simple PLDs. There is also a range of CPLD (Complex PLD) packages available.

More on the Programmable Devices (continued…) These CPLD structures can look something like:

More on the Programmable Devices (continued…) A series of switches used to link the different packages used to construct this CPLD. Programming these devices is either done by the same method as PROMs or can be programmed through memory elements that are linked to the switches (transistor connecting different lines) every time at power up. This gives us some of the features seen in volatile memory. This structure looks like:

More on the Programmable Devices (continued…) FPGA (Field Programmable Gate Array) is a similar logic that looks like this:

More on the Programmable Devices (continued…) Again here we have the ability to both program the logic blocks and also the switching network in between it. Only here the logic blocks have reduced in size that gives us more flexibility in design whereas the size of the switching network has increased bringing more delay in our design. A number of I/O blocks will be used around CPLDs or FPGAs that are programmed individually in order to connect these to the outside wourld.

More on the Transistor Structure A transistor has two structure parameters, its width and its length. The larger the length the more common space between its two drift areas and the more current passes through. This more current is sometimes needed and we have to trade larger current for space we lose when making the transistor bigger.

Computer Aided Design In packages such as FPGAs programming can become impossible when complicated functions with a large number of inputs are needed. This is computer aided design through the following steps can be handy: Write Verilog Simulate and verify design (Model Sim or Silos). Here verification means checking waveforms to see whether or not they satisfy our needs, and if they don’t we return to step one.

Computer Aided Design (continued…) Synthesize, generate net list (Leonardo). This gives us a net list of the hardware needed in the target technology. This step can sometimes include a post synthesis simulation and verification that is this time done with exact timing features of the chosen devices. Device Bit Stream (Quartus). It gives us a method to program the specific device we are using. Program device (Quartus).