Presentation on theme: "Field Programmable Gate Array"— Presentation transcript:
1 Field Programmable Gate Array FPGAField Programmable Gate ArrayWith an overview of different Reconfigurable TechnologiesPresented by:Ramtin Raji Kermani(Senior student of Computer EngineeringShiraz UniversitySpring 2006Image courtesy of:
2 Application Specific Integrated Circuits (ASICs) Covered subjectsWhat is Reconfigurable Computing?Application Specific Integrated Circuits (ASICs)Programmable Logic Devices (PLDs)Programmable Logic Arrays (PLAs)Field Programmable Gate Array : FPGAWhy FPGA?FPGA ArchitectureFPGA ImplmentationFPGA design ProcessHardware Description Languages : HDLs
3 What is Reconfigurable Computing? Concept from 1960’s, But still a new field of research.The ability to change the Processing unit at Run-Time.Computer processing with highly flexible computing fabrics.The ability to changes the data path, in addition to the control flow.Run-Time and On-board reconfiguration Software FlexibilityHardware SpeedA Computer consisting:A Standard processorAn array of reconfigurable hardwareInitial Ideas …The main processor would control the behavior of the reconfigurable hardware. The reconfigurable hardware would then be tailored to perform a specific task, such as image processing or pattern matching, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task.
4 What is Reconfigurable Computing? Reconfigurable Logic Characteristics:1. Granularity: size of the smallest functional unit (CLB)Low granularity (Fine-Grained) : like FPGAsGreater FlexibilityIncreased power, delay, area due to greated Qtty. of routingBit level manipulationHigh granularity (Coarse-grained) : like rDPAsConsists of big elementsOptimized for standard data path applicationsDrawback: loosing some of its utilisation for smaller computationsWord-with data pathsA larger block instead of smaller connected unitsrDPU: Reconfigurable Data Path Units
5 What is Reconfigurable Computing? Reconfigurable Logic Characteristics:2. Rate of Configuration:Reconfiguration can happen at deployment timeBetween execution or During execution (at Run-Time)Bit streams is used t reprogram the device at Deployment timeFine grained systems require more config. TimePartial Reconfiguration: A part is being reconfgured while the other is performing3. Routing / Interconnects:Flwxibility of a Reconfigurable Device come from its routing interconnectsIsland Style Layout: Blocks in Vertical and Horizental routing (in FPGAs)
6 What is Reconfigurable Computing? Island Style layout
7 Application Specific Integrated Circuits : ASICs Used to design a system on a chipTo do a VERY specific job, no reconfigurationInterconnect of standard cellsHighly automated design flowASICs design flow:RTL descriptionFunctional simulationSynthesisDesign verificationLayout
8 Processors Vs. ASICs Processors: ASICS: Take longer to compute Slow FlexibleNeed instructions to determine what to do on each cycleASICS:Take shorter time to computeFastNot FlexibleNo instructionSame calculation every cycle
9 Actual computation Processors Vs. ASICs Processor ASIC The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array.Actual computationProcessorASIC
10 ? Slow Flexible Fast Inflexible Reconfigurable Computing Processors Vs. ASICsTemporalSpatialSingleProcessorASICSlowFlexibleFastInflexibleReconfigurableComputing?The main processor would control the behavior of the reconfigurable hardware. The reconfigurable hardware would then be tailored to perform a specific task, such as image processing or pattern matching, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task.
11 Programmable array logic: PAL A programmable Logic DeviceUsed to implement combinational logic circuitsFirst introduced by Monolithic Memories Inc. (MMI) in 1978Priviously FPLA by Signetics (1975)
12 Field programmable Gate Arrays dimensional array of logic blocks and flip-flopswith a electrically programmable interconnectionsFPGA provides its user a way to configure:The intersection between the logic blocksThe function of each logic block.FPGA Logic Blocks can be configured to offer functions:As simple as a transistorAs Complex as a CPU
15 FPGAs has four different logic block structures: FPGA Logic BlocksFPGAs has four different logic block structures:Crosspoint FPGAPlessey FPGAActel Logic BlockXilinx Logic block
16 Crosspoint FPGACrosspoint FPGA: consist of two types of logic blocks. One is transistor pair tiles in which transistor pairs run in parallel lines as shown in figure below:
17 Plessey FPGAPlessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.
18 Actel Logic BlockActel Logic Block: If inputs of a multiplexer are connected to a constant or to a signal, it can be used to implement different logic functions.
19 Xilinx Logic block:Xilinx Logic block: Look up table is used to implement any number of different functionality.
20 SRAM programming technology Static RAM cells are used to control pass gates or multiplexers
21 Floating Gate Programming The programmable switch is a transistor that permanently be disabled
22 The FPGA design process of xillinx products are as follows: FPGA Design FlowThe FPGA design process of xillinx products are as follows:(the other products have similar process)For more info :
23 Hardware Description Languages: HDLs For programming FPGAs, we need a special kind of programming language to describe hardware functions.Three Major HDLs:VHDL (VHSIC Hardware Description Language)VeriLogJHDL (Java implementation as HDL)
24 References As Always: My dear GoOgLe : www.google.com !!! Introduction to Reconfigurable Computing, Hayden SoDigital Logic Circuit Analysis & Design, V.NelsonXILINX documentationsACTEL documentation