1. Digital Design: Combinational Logic Blocks
Credits:
Slides adapted from:
J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006
C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004
A.B. Marcovitz, Intro. to Logic and Computer Design, McGraw Hill, 2008
R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

2. Multiplexers (Data Selectors)
A multiplexer (MUX for short) is a digital switch:
it passes (connects) one of its data inputs to the output.
the data input selected is a function of a set of control inputs called selection inputs.
I1 I0 A Z
A Z 0 I0 1 I1
Two alternative forms
for a 2:1 Mux truth table
Z = A' I0 + A I1

3. Multiplexers (cont’d)

4. Gate level implementation of muxes

5. Cascading multiplexers
Large multiplexers can be made by cascading smaller ones
I0 I1 I2 I3
I4 I5 I6 I7
4:1 mux
2:1 mux
8:1 mux
alternative implementation
4:1 mux
2:1 mux
I4 I5
I2 I3
I0 I1
I6 I7
8:1 mux Z Z
B C A
Control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7
Control signal A chooses which of the upper or lower mux's output to gate to Z C
A B

6. Multiplexers as general-purpose logic
A 2n:1 multiplexer can implement any function of n variables
with the variables used as control inputs and
the data inputs tied to 0 or 1
Example:
F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABC F C A B S2
8:1 MUX S1 S0 Z
= A'B'C'(1) + A'B'C(0) + A'BC'(1) + A'BC(0) +
AB'C'(0) + AB'C(0) + ABC'(1) + ABC(1)
Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

7. Multiplexers as general-purpose logic (cont’d)
Generalization data inputs can also be tied to variables not just 0’s an 1’s
I0 I In-1 In F In In' 1
four possible
configurations of truth table rows can be expressed as a function of In
n-1 mux control variables
single mux data variable

8. Activity Realize F = B’CD’ + ABC’ with a 4:1 multiplexer 0 when B’C’
A B C D Z
0 when B’C’
D’ when B’C
A when BC’
0 when BC B C S1 S0 F
4:1 MUX
0 D’ A 0
Z = B’C’(0) + B’C(D’) + BC’(A) + BC(0)

9. Multiplexer with bus inputs and outputs

10. Demultiplexers
Route a single input to one of many outputs, as a function of a set of control inputs 3 x y0 y1 y2 y3 y4 y5 y6 y7
s[2:0]
1:8
demux

11. Three-State Buffers
Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other (multiple drivers conflict).
Use of tri-state logic permits the outputs of two or more gates or other logic devices to be connected together 1 B1 ?
The two driving blocks fight
with each other B2
(buffers are a.k.a. drivers)

12. Tri-state Buffers (cont’d)
When the enable B is 1, the output C equals A.
When the enable B is 0, the output C acts like an open circuit.
In this case the output C is effectively disconnected from the
buffer output so that no current can flow.
This is often referred as Hi-Z (high-impedance) state because
the circuit offers a very high impedance to the flow of current.

13. Tri-state Buffers application examples

14. Tri-state Buffers application examples (cont’d)

15. Tri-state buffers application examples (cont’d)

16. Tri-state Buffers application examples (cont’d)

17. Decoders
A decoder is a logic circuit that converts coded inputs into coded outputs.
Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs)

18. Decoders (cont’d)
Decimal

19. Binary Decoders
The most common decoder circuit is an n-to-2n decoder (or binary decoder)

20. Binary Decoders (cont’d)

21. Binary Decoders (cont’d)

22. Gate level implementation of decoders
active-high enable O0 G S O1
active-low enable O0 \G S O1
1:2 decoders
2:4 decoders
active-high enable S1 O2 O3 O0 G O1 S0
active-low enable S1 O2 O3 O0 \G O1 S0

23. Decoders as general-purpose logic
n-to-2n decoders can implement any function of n variables
with the variables used as control inputs
the appropriate minterms summed to form the function
decoder generates appropriate
minterm based on control signals
(it "decodes" control signals)
A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC C A B S2
3:8 DEC S1 S0

24. Decoders as general-purpose logic (cont’d)
0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD F1
F1 = A'BC'D + A'B'CD + ABCD
F2 = ABC'D' + ABC
F3 = (A' + B' + C' + D')
4:16 DEC F2 F3 A B C D

25. Encoders An encoder performs the inverse function as a decoder
The simplest encoder to build is a 2n-to-n (binary encoder)

26. Priority Encoders I7 I6 I5 I4 I3 I2 I1 I0 A2 A1 A0
IDLE 1 x

27. Priority Encoders (cont’d)

28. Programmable Arrays ROM (read only memories)
PLA (programmable logic array)
PAL (programmable array logic)
CPLD (complex programmable logic devices)
FPGA (field programmable gate arrays)

29. Read-Only Memories (ROM)
A ROM consists of a two dimensional array of semiconductor devices interconnected to store an array of binary data
Two-level canonical form combinational logic can be implemented using a ROM as a look-up-table (LUT)
truth table
A B C F0 F1 F2 F3
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'

30. Combinational logic using a ROM

31. ROM Structure
2n words

32. PLA (Programmable Logic Arrays)
A PLA performs the same basic LUT task as a ROM.
A PLA with n inputs and m outputs can realize m combinational functions of n variables.
The internal organization of a PLA is different from that of the ROM

33. PLA (cont’d)

34. PLA short-hand notation

35. Activity Map the following functions to the PLA below:
W = AB + A’C’ + BC’
X = ABC + AB’ + A’B
Y = ABC’ + BC + B’C’ A B C W X Y

36. Activity (cont’d) 9 terms won’t fit in a 7 term PLA
Manipulating logic functions
so that they can use available
resources is called
Technology Mapping
9 terms won’t fit in a 7 term PLA
can apply concensus theorem to W to simplify to: W = AB + A’C’
8 terms wont’ fit in a 7 term PLA
observe that AB = ABC + ABC’
can rewrite W to reuse terms: W = ABC + ABC’ + A’C’
Now it fits
W = ABC + ABC’ + A’C’
X = ABC + AB’ + A’B
Y = ABC’ + BC + B’C’ A B C W X Y
ABC
ABC’
A’C’
AB’
A’B BC
B’C’

37. PAL (Programmable Array Logic)
The PAL is a special case of the PLA in which the AND array is programmable and the OR array is fixed
Figure. PAL Segment

38. Implementation of a Full Adder Using a PAL

39. CPLDs and FPGAs The distinction between CPLD and FPGAs is blurred.
CPLDs contain a matrix of logic macrocells that usually consist of programmable array logic followed
by a flip-flop or latch. The macrocells are connected
using a single large programmable interconnect block
FPGAs contain a regular
structure of programmable basic
logic cells surrounded by
programmable interconnect.

40. Example of CPLD Internal Structure

41. Example of FPGA Internal Structure