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Memory and Programmable Logic

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Presentation on theme: "Memory and Programmable Logic"— Presentation transcript:

1 Memory and Programmable Logic
Chapter 7

2 Introduction RAM: Random Access Memory ROM: Read Only Memory
Write operation: Storing info into memory Read operation: Transferring info out of the memory RAM can perform both Write and Read operations ROM is a Programmable Logic Device (PLD) that can be written once and can only be read afterwards PLA: Programmable Logic Array PAL: Programmable Array Logic FPGA: Field Programmable Gate Array

3 Conventional and array logic diagrams

4 Random Access Memory Memory unit that can be written or read
Memory is composed of “words” Word is a group of bits Byte is a group of 8 bits (Denoted B) Words can have one or more bytes: a word of 32 bits has 4 bytes Memory size is normally measured in bytes, e.g., 1024 bytes = 1KB

5 Random Access Memory When word size is known memory size can be given in words, e.g., 1 word = 64 bits = 8 bytes. 1K requires 10 bits address, i.e., 1024 = 210 1M = 220 1G = 230 4G = 232 Each word has an id. number called an address (0 to 2k`-1, where k is the # of address lines)

6 Random Access Memory

7 Random Access Memory Contents of a 1K x 16 memory

8 Write and read operations
Read and write take the same time, regardless of location; contrast with magnetic tape; read may take different time from write operation Write: transfer-in operation Read: transfer-out operation

9 Write and read operations
Steps to store a new word into memory Apply binary address of desired word to address lines (k) Apply data bits that must be stored in memory to data input lines (nin) Activate the write input Memory unit will take bits from input data lines and store them in word specified by address lines

10 Write and read operations
Steps to read a word out of memory Apply desired binary address of desired word to address lines Activate the read input Memory unit will take bits from word specified by address lines and apply them to output data lines

11 Write and read operations
Control inputs in typical commercial memory chips

12 Timing waveforms Cycle time: time required to finish a write operation

13 Timing waveforms access time: time required to finish a read operation

14 Timing waveforms CPUCLK T = 1/fCLK Cycle Time (i.e. Write Time)

15 Types of memories Static RAM or SRAM: consists of internal latches that store binary information Dynamic RAM or DRAM: stores information in form of electric charge on capacitors provided by MOS transistors inside the chip, thus requires refresh every few ms Volatile memory lose stored information when powered off. Magnetic memory is nonvolatile. ROM is another type of nonvolatile memory

16 Types of memories DRAM refreshing requires cycling through words every few ms to restore decaying charge DRAM offers reduced power consumption and larger storage capacity in a single chip SRAM is easier to use Bonus Assignment: find out what Flash Memories are and how they are used

17 Memory Decoding

18 Memory Decoding

19 Coincident decoding LSB
Decoder with k inputs and 2k outputs requires 2k AND gates A 1K memory requires a 10x1024 decoder Use instead a 2-D selection patter and 1K requires two 5x32 decoders! Word is selected by coincidence of one X and one Y line MSB

20 Address multiplexing SRAMs contain 6 transistors per cell
DRAMs contain one MOS transistor and one capacitor per cell DRAMs achieve higher storage capacity per unit area – four times that of a SRAM - and lower power consumption DRAM typical word size = 1 bit DRAM is preferred for large memories for PCs DRAM available from 64K to 256M bits To reduce number of pins, thus chip size, use address multiplexing

21 Address multiplexing Capacity = 256x256 = 28x28 =64K
RAS = Row Address Strobe CAS = Column Address Strobe

22 Error Detection and Correction
Dynamic physical interaction of electrical signals may cause occasional errors Memories can use two types of codes: Error detection codes, parity (chapter 3) Error correction codes

23 Error Detection and Correction
Hamming code Error correction code Uses several parity bits per word Can detect and correct 1-bit errors

24 Hamming code Bit position 1 2 3 4 5 6 7 8 9 10 11 12 P1 P2 P4 P8
P8 Parity generation equations 𝑃 1 =𝐸𝑋𝑂𝑅(3,5,7,9,11) 𝑃 2 =𝐸𝑋𝑂𝑅(3,6,7,10,11) 𝑃 4 =𝐸𝑋𝑂𝑅(5,6,7,12) 𝑃 8 =𝐸𝑋𝑂𝑅(9,10,11,12) Check bit equations (Syndrome) 𝐶 1 =𝐸𝑋𝑂𝑅(1,3,5,7,9,11) 𝐶2=𝐸𝑋𝑂𝑅(2,3,6,7,10,11) 𝐶 4 =𝐸𝑋𝑂𝑅(4,5,6,7,12) 𝐶 8 =𝐸𝑋𝑂𝑅(8,9,10,11,12)

25 Hamming code Bit 1 2 3 4 5 6 7 8 9 10 11 12 No error Bit 1 error
Bit 1 error Bit 5 error

26 Hamming code Syndrome Position of error C8 C4 C2 C1 No error 1 2 3 4 5
1 2 3 4 5 6 7 8 9 10 11 12

27 Single-error correction, double-error detection

28 Read-Only Memory

29 Read-Only Memory

30 Read-Only Memory

31 Read-Only Memory ROM programming according to table 7.3

32 Combinational circuit implementation
ROM uses a decoder for address and decoder gives minterms Outputs use OR gates thus ROM can be seen as: A storage device Combinational circuit implementing Boolean functions

33 Combinational circuit implementation Example
Example 7.1: ROM-based circuit that accepts a three-bit number and produces a binary number equal to the square of the input number.

34 Combinational circuit implementation Example

35 Types of ROM Mask programming: done by semicondutor company during last fabrication process of unit PROM (Programmable ROM): Programming by blowing fuses by applying a high voltage; blown fuse outputs a 0 EPROM (Erasable PROM): Erase using special ultraviolet light EEPROM or E2PROM (Electrically Erasable PROM)

36 Combinational PLDs

37 Programmable Logic Array
Exercise: Obtain the equations for this PLA. What role do the EXOR gates play?

38 Programmable Logic Array

39 Example 7.2 Implement the following two Boolean functions with a PLA:
𝐹 1 𝐴,𝐵,𝐶 = 0,1,2,4 𝐹 2 𝐴,𝐵,𝐶 = 0,5,6,7 What do we have to do? Obtain minimum number of terms as sum of products 𝐹 1 𝐴,𝐵,𝐶 = 𝐴 ′ 𝐵′+𝐴 ′𝐶 ′ +𝐵′𝐶′ 𝐹 2 𝐴,𝐵,𝐶 =𝐴𝐵+𝐴𝐶+𝐴′𝐵′𝐶′

40 Programmable Array Logic

41 Example of PAL Programming

42 Example of PAL Programming

43 Sequential Programmable Devices

44 Sequential Programmable Devices
SPLD: Sequential Programmable Logic Device CPLD: Complex Programmable Logic Device

45 Sequential Programmable Devices
Basic macrocell logic

46 Sequential Programmable Devices

47 Sequential Programmable Devices
Architecture of Xilinx Spartan FPGA (Field Programmable Gate Array

48 Sequential Programmable Devices
Configurable Logic Block (CLB)

49 Sequential Programmable Devices
RAM cell controlling a PIP transmission gate

50 Exercises 7.1 7.2 7.3 7.4 7.6 7.7 7.8 7.9 7.10 7.14 7.15 7.18 7.19 7.20 7.23 7.24

51 P7.26

52 Sequential Programmable Devices
IOB of XC4000 Series

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