1. ECE434a Advanced Digital Systems L02
Electrical and Computer Engineering University of Western Ontario

2. Outline What we know What we do not know
Laws and Theorems of Boolean Algebra
Simplification of Logic Expressions
What we do not know
How to use K-maps for 5, 6 variables
How to design using only NAND or only NOR gates
What are tri-state buffers for
What are basic combinational building blocks
Multiplexers
Decoders
Encoders
How to implement functions using ROMs, PLAs, and PALs
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3. Review: Laws and Theorems of Boolean Algebra
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4. Review: Laws and Theorems of Boolean Algebra
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5. Review: Simplifying Logic Expressions
Combining terms
Use XY+XY’=X, X+X=X
Eliminating terms
Use X+XY=X
Eliminating literals
Use X+X’Y=X+Y
Adding redundant terms
Add 0: XX’
Multiply with 1: (X+X’)
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6. Review: Karnaugh Maps Example Sum of products Product of sums
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7. Five variable Karnaugh MapBC BC 00 01 11 10 00 01 11 10 DE DE 00 00 1 1 1 01 1 1 01 1 1 1 1 11 11 1 1 1 1 10 10
A=0
A=1
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8. Six Variable Karnaugh Map1 00 01 11 10 CD EF 1 00 01 11 10 CD EF
AB=00
AB=01 1 00 01 11 10 CD EF 1 00 01 11 10 CD EF
AB=10
AB=11
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9. Designing with NAND and NOR Gates (1)
Implementation of NAND and NOR gates is easier than that of AND and OR gates (e.g., CMOS)
Why? Based on VLSI transistor.
Which is the optimal NAND gates?
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10. Designing with NAND and NOR Gates (2)
Any logic function can be realized using only NAND or NOR gates => NAND/NOR is complete
NAND function is complete – can be used to generate any logical function;
1: a I (a | a) = a | a’ = 1
0: {a I (a | a)} | {a I (a | a)} = 1 | 1 = 0
a’: a | a = a’
ab: (a | b) | (a | b) = (a | b)’ = ab
a+b: (a | a) | (b | b) = a’ | b’ = a + b
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11. Conversion to NOR Gates
Start with POS (Product Of Sums)
circle 0s in K-maps
Find network of OR and AND gates
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12. Conversion to NAND Gates
Start with SOP (Sum of Products)
circle 1s in K-maps
Find network of OR and AND gates
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13. Tristate Logic and Busses
Four kinds of tristate buffers
B is a control input used to enable and disable the output
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14. Data Transfer Using Tristate Bus
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15. Combinational-Circuit Building Blocks
Multiplexers
Decoders
Encoders
Code Converters
Comparators
Adders/Subtractors
Multipliers
Shifters
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16. Multiplexers: 2-to-1 Multiplexer
Have number of data inputs, one or more select inputs, and one output
It passes the signal value on one of data inputs to the output s w w f s w f 1 1 w
(a) Graphical symbol 1
(c) Sum-of-products circuit s f w 1 w 1
(b) Truth table
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17. Multiplexers: 4-to-1 Multiplexers s s s f 1 1 w w 00 w s w 1 1 01 1 w f w 1 2 10 1 w w 2 11 w 3 1 1 w 1 3 f
(a) Graphic symbol
(b) Truth table w 2 w 3
(c) Circuit
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18. Multiplexers: Building Larger Mulitplexerss s 1 1 s w w 3 w w 1 1 w s 4 2 s 3 f w 1 7 w f 2 w 3 1 w 8 w 11
(a) 4-to-1 using 2-to-1
(b) 16-to-1 using 4-to-1 w 12 w 15
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19. Synthesis of Logic Functions Using Muxesw w w f 2 1 2 w 1 1 1 1 f 1 1 1 1 1
(a) Implementation using a 4-to-1 multiplexer w w f 1 2 w f 1 w 1 w 2 1 1 1 w w 2 2 1 1 f 1 1
(b) Modified truth table
(c) Circuit
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20. Synthesis of Logic Functions Using Muxesw w w f 1 2 3 w w f 1 2 1 w 1 3 1 w 1 3 w 1 1 1 1 1 1 2 w 1 1 1 1 1 w 1 1 1 3 f 1 1 1 1 1
(a) Modified truth table
(b) Circuit
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21. Decoders: n-to-2n Decoder
Decode encoded information: n inputs, 2n outputs
If En = 1, only one output is asserted at a time
One-hot encoded output
m-bit binary code where exactly one bit is set to 1 w y n 2 n
inputs w
outputs n – 1 y
Enable En 2 n – 1
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22. Decoders: 2-to-4 DecoderEn w w y y y y 1 1 2 3 w 1 1 y 1 1 1 w 1 1 1 1 1 1 1 1 x x y 1
(a) Truth table y 2 w y w y 1 1 y 3 y 2 y En En 3
(c) Logic circuit
(b) Graphic symbol
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23. Decoders: 3-to-8 Using 2-to-4w w y y w w y y 1 1 1 1 y y 2 2 w 2 En y y 3 3 En w y y 4 w y y 1 1 5 y y 2 6 En y y 3 7
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24. Decoders: 4-to-16 Using 2-to-4w w y y w w y y 1 1 1 1 y y 2 2 En y y 3 3 w y y 4 w y y 1 1 5 y y 2 6 w 2 w y y y En 3 7 w w y 3 1 1 y 2 En y w y y En 3 8 w y y 1 1 9 y y 2 10 En y y 3 11 w y y 12 w y y 1 1 13 y y 2 14 En y y 3 15
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25. Encoders Opposite of decoders Binary encoders
Encode given information into a more compact form
Binary encoders
2n inputs into n-bit code
Exactly one of the input signals should have a value of 1, and outputs present the binary number that identifies which input is equal to 1
Use: reduce the number of bits (transmitting and storing information) w y n n 2
outputs
inputs y w n – 1 2 n – 1
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26. Encoders: 4-to-2 Encoderw w w w y y 3 2 1 1 w 1 w 1 1 1 y 1 1 w 1 1 1 2 y w 1 3
(a) Truth table
(b) Circuit
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27. Encoders: Priority Encoders
Each input has a priority level associated with it
The encoder outputs indicate the active input that has the highest priority
(a) Truth table for a 4-to-2 priority encoder w w w w y y z 3 2 1 1 d d 1 1 1 x 1 1 1 x x 1 1 1 x x x 1 1 1
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28. Code Converters
Convert from one type of input encoding to a different output encoding
E. g., BCD-to-7-segment decoder w w w w a b c d e f g 3 2 1 a a 1 1 1 1 1 1 b w 1 1 1 c f b w 1 1 1 1 1 1 1 d w 2 g 1 1 1 1 1 1 1 e e c w 3 1 1 1 1 1 f g 1 1 1 1 1 1 1 d 1 1 1 1 1 1 1 1
(a) Code converter
(b) 7-segment display 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(c) Truth table
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29. Extension of Digital Design Fundamental
What is the optimization?
Synthesis
Design project 1:
Optimization based on majority gate
Modified K-map based on majority gate
Optimization based on pass gate
Modified K-map based on pass gate
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30. Programmable Logic Devices
Read Only Memories (ROMs)
Programmable Logic Arrays (PLAs)
Programmable Array Logic Devices (PALs)
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31. Read-Only Memories Store binary data
data can be read out whenever desired
cannot be changed under normal operating conditions
n input lines, m output lines => array of 2n m-bit words
Input lines serve as an address to select on of 2n words
Use ROM to implement logic functions?
n variables, m functions
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32. Basic ROM Structure
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33. ROM Types Mask-programmable ROM EPROM (Erasable Programmable ROM)
Data is permanently stored (include or omit the switching elements)
Economically feasible for a large quantity
EPROM (Erasable Programmable ROM)
Use special charge-storage mechanism to enable or disable the switching elements in the memory array
PROM programmer is used to provide appropriate voltage pulses to store electronic charges
Data is permanent until erased using an ultraviolet light
EEPROM – Electrically Erasable PROM
erasure is accomplished using electrical pulses (can be reprogrammed typically 100 to 1000 times)
Flash memories - similar to EEPROM except they use a different charge-storage mechanism
usually have built-in programming and erase capability, so the data can be written to the flash memory while it is in place, without the need for a separate programmer
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34. Programmable Logic Arrays (PLAs)
Perform the same function as a ROM
n inputs and m outputs – m functions of n variables
AND array – realizes product terms of the input variables
OR array – ORs together the product terms
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35. PLA: 3 inputs, 5 p.t., 4 outputs
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36. nMOS NOR Gate
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37. AND-OR Array Equivalent
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38. To Do Textbook Read Design Project 1: majority gate and pass gate
Chapter 1.3, 1.4, 1.13
Read
Altera’s MAX+plus II and the UP1 Educational board: A User’s Guide, B. E. Wells, S. M. Loo
Altera University Program Design Laboratory Package
Design Project 1: majority gate and pass gate
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