1. Lecture 2: Field Programmable Gate Arrays September 13, 2004 ECE 697F Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays

2. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Overview Three types of FPGAs -EEPROM -SRAM -Antifuse SRAM FPGA architectural choices. FPGA logic blocks -> size versus performance. FPGA switch boxes State-of-the-art -Research issues in architecture.

3. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Configuration vs. programming °FPGA configuration: Bits stay at the device they program. A configuration bit controls a switch or a logic bit. °CPU programming: Instructions are fetched from a memory. Instructions select complex operations. CPUmemory add r1, r2IRadd r1, r2

4. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Logic element questions °How many inputs? °How many functions? All functions of n inputs or eliminate some combinations? What inputs go to what pieces of the function? °Any specialized logic? Adder, etc. °What register features?

5. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Anti-Fuse FPGA (Actel ACT family) Anti-fuses are one-time programmable. -16 Volt pulse eliminates dielectric -Only need to program once. High performance -> direct connections between poly and N+ Less appropriate for Reconfigurable Computing -Good for bus transceivers -High speed operation.

6. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Antifuses °Permanently programmed. °Make a connection with electrical signal. More reliable than breaking a connection. Avoids shrapnel. °Resistance of about 100 .

7. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Antifuse structure substrate Metal 1 Metal 2 antifuse via

8. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Rows of programmable logic building blocks + rows of interconnect Anti-fuse Technology: Program Once 8 input, single output combinational logic blocks FFs constructed from discrete cross coupled gates Use Anti-fuses to build up long wiring runs from short segments I/O Buffers, Programming and Test Logic Logic ModuleWiring Tracks I/O Buffers, Programming and Test Logic Actel Programmable Gate Arrays

9. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Actel Logic Module

10. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Interconnection Fabric Actel Interconnect

11. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Jogs cross an anti-fuse minimize the # of jogs for speed critical circuits 2 - 3 hops for most interconnections Actel Routing Example

12. Lecture 2: Field Programmable Gate Arrays September 13, 2004 EEPROM Devices (PLDs) Frequently used technology for PALs, GALs, EPLDs User design frequently decomposed into SOP representation Appropriate for system glue logic. Single transistor interconnection point.

13. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Altera Max 7000 Macrocell

14. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Max 7000 PLD Structure

15. Lecture 2: Field Programmable Gate Arrays September 13, 2004 SRAM-based FPGA SRAM bits can be programmed many times Each programming bit takes up five transistors Larger device area reduces speed versus EPROM and antifuse. Read or Write Data Q Q Programming Bit I1I2 P1 P2 P3 P4 Out 2-Input LUT

16. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Field Programmable Gate Array

17. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Design Tradeoffs Some logic clusters are large (e.g. Altera/Xilinx contains 8-10 LUT-FF pairs) Three important issues: -Logic elements per cluster -Cluster connectivity to interconnect – wires (F C ) – connection flexibility -Switchbox flexibility (F s ) Logic Cluster IO connections switchbox

18. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Issue 1: The Logic Cluster Question: How many BLE should there be per cluster?

19. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Logic cluster utilization (Betz & Rose) °Logic utilization vs. fraction of inputs accessible to LE in cluster. °Utilization at 100% when only 50%-60% of inputs are accessible. °Also found that connecting each track to only one LE output per cluster was sufficient. © 1998 IEEE

20. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Area efficiency vs. cluster size (Betz & Rose) °Transistors per LE vs. cluster size. Includes overhead circuits. °Clusters in size 1-8 were area-efficient. © 1998 IEEE

21. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Logic Cluster Size Interestingly, small block cluster more efficient (Betz – CICC’99) Includes area needed for routing. Small clusters (e.g. one BLE per cluster) not “CAD friendly). Most commercial devices have 4-10 BLEs per cluster

22. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Number of Inputs per Cluster Lots of opportunities for input sharing in large clusters (Betz – CICC’99) Reducing inputs reduces the size of the device and makes it faster. Most FPGA devices have more inputs than actually needed to allow for routing flexibility

23. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Connection Box Flexibility F c -> How many tracks does an input pin connect to? If logic cluster is small, F C is large F C = W If logic cluster is large, F c can be less. -Approximately 0.2W for Xilinx XC4000EX, Virtex Logic Cluster IO pin Tracks Out T0T0 T1T1 T2T2 T0T0 T1T1 T2T2 F C = 3 T0T0 T1T1 T2T2

24. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Switchbox Flexibility Switch box provides optimized interconnection area. Flexibility found to be not as important as F C Six transistors needed for F S = 3 0 1 0 1 01 01

25. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Putting it all together Xilinx XC4000EX family -F S = 3 -F C = 0.2 -I = 8 Altera Flex10K family -F S = 3 -F C = 0.25 -I = 22 More contemporary FPGAs have larger cluster sizes and segmentation. More difficult to quantify exact F c and F s values.

26. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Switchbox Issues

27. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Switch Matrix

28. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Xilinx 4000 Interconnect Details

29. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Wilton Switchbox Rotate connections inside the switchbox while keeping F S = 3 Still has six transistors for base switch matrix. Eliminates domain issue 021 2 0 1 2 0 1 021

30. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Switchbox Issues

31. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Buffering FPGAs need to buffer to isolate large RC networks Architects must decide where to place buffers. SS

32. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Segmentation Segmentation distribution: how many of each length? Longer length -Better performance? -Reduced routability?  XY Length 4 Length 2 Length 1

33. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Translating a Design to an FPGA Hierarchical FPGA likely to have a tree-like interconnect. Each “sub-array” contains about 100K gates Clever VLSI layout needed FPGA

34. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Pipelined Interconnect Latest trend in FPGAs is to embed clocked flip flops in device to pipeline data. Helps create tolerance for delay Allows interconnect to be reused Large FPGA looks like a parallel processor. FPGA

35. Lecture 2: Field Programmable Gate Arrays September 13, 2004 FPGA Comparison

36. Lecture 2: Field Programmable Gate Arrays September 13, 2004 Summary Three basic types of FPGA devices -Antifuse -EEPROM -SRAM Key issues for SRAM FPGA are logic cluster, connection box, and switch box. Latest advances examine performance and routability. Next class: FPGA versus Processor