1. EKT 221 Digital Electronics II
CHAPTER 3 : Memory Basics

2. Today’s Outline Memory Basics Memory Definitions Memory Organizations
RAM – Static RAM (SRAM)

3. Memory Definitions
Collection of cells capable of storing binary information
Contains electronic circuits for storing & retrieve information
Used to provide temporary or permanent storage capability

4. Memory Basic Process
Info/content from memory is send to h/w (usually consist of registers & combinational logic) to be processed
The processed info is then returned to the same or different memory address
Input and Output devices may also interact with memory
Memory
Hardware
for
processing
I/O
Printers
Mouse
Keyboard
Monitor
Digital Camera
Scanners
Plotters
Thumb Drive
External Memory

5. Types of Memories Random Access Memory (RAM)
Write operation – stores new info
Read operation – transfer the stored info out of memory
Read Only Memory (ROM)
Perform read operation only

6. Memory data elements Typical data elements are:
bit : a single binary digit
byte : a collection of eight (8) bits accessed together
word : a collection of binary bits whose size is a typical unit of access for the memory. (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)
Memory Data ─ a bit or a collection of bits to be stored into or accessed from memory cells.
Memory Operations ─ operations on memory data supported by the memory unit. Typically, read and write operations over some data element (bit, byte, word, etc.).

7. Memory Organization
Organized as an indexed array of words. Value of the index for each word is the memory address.
Often organized to fit the needs of a particular computer architecture. Some historically significant computer architectures and their associated memory organization:
Digital Equipment Corporation PDP-8 (DEC Alpha)
used a 12-bit address to address bit words.
IBM 360
used a 24-bit address to address 16,777,216 8-bit (bytes), or
4,194, bit words.
Intel 8080 (8-bit predecessor to the 8086 and the current Intel processors)
used a 16-bit address to address 65,536 8-bit (bytes).

8. Memory Block Diagram A basic memory system is shown here:
k address lines are decoded to address 2m words of memory.
Each word is n bits.
Read and Write are single control lines defining the simplest of memory operations.
K Address Line m
2m Words
n bits per Word
(Refer to next slide for example)

9. Memory Organization Example of memory contents above:
K Address Line m
2m Words
n bits per Word
Example of memory contents above:
address bits = 3; m = 3
data bits = 8; n = 8
Therefore number of address lines = k = (2m); 23 = 8
Address range = 0 to 2m -1; therefore 0 to 23 – 1, Address range = 0 to 7
1 word is the size of the memory content; so the memory above has 8 words of 8-bit data

10. Memory Organization Example: address bits = m = 10
data bits =16; n = 16
Address line = (2m)
210 = 1024 or 1K, labeled 0 to 1023
memory content = 16-bit
so the memory has 1K words of 16-bit data or 1K x 16-bit memory
Note :
K (Kilo) = 210
M (Mega) = 220
G (Giga) = 230
Other Example :
64K = 216 = (26 * 210)
2M = = (21 * 220)
4G = = (22 * 230)
What is the address bits (m)?

11. Memory Operations Memory operations require the following:
Data
Address
An operation ─ Typical operations are READ and WRITE. (RAM)
Read Memory ─ an operation that reads a data value stored in memory: (takes from memory)
Place a valid address on the address lines
Activate the Read input.
Note : the content of the selected word are not changed by reading them
Write Memory ─ an operation that writes a data value to memory:
Apply data on the data lines
Activate the Write input
Other than Read/Write (R/W) Chip Select is used to enable a particular RAM. It is sometimes called Memory Enable.

12. Memory Enable

13. RAM Integrated Circuit
Types of random access memory (RAM)
Static – information stored in latches
Dynamic – information stored as electrical charges on capacitors
Charge “leaks” off
Periodic refresh of charge required
Dependence on Power Supply
Volatile – loses stored information when power turned off (example : FPGA – Flex10K)
Non-volatile – retains information when power turned off (example : CPLD – MAX)

14. RAM : Cell Arrays and Coincident Selection
Memory arrays can be very large =>
Large decoders
Large fanouts for the bit lines
However, the decoder size and fanouts can be reduced by using a coincident selection in a 2-dimensional array:
Uses two decoders, one for words and one for bits
Word select becomes Row select
Bit select becomes Column select

15. Example: Coincident Selection 16 X 1 RAM Chip
16 = 24 = 4 bit add.[A3..A0]
The column decoder is enabled with the CS input
When CS =0, column decoder is disabled and all o/p are 0 and NONE of the cells are selected
A3 and A2 used for Row select
A1 and A0 for Column select
Figure : 9.7
Morris Mano, pg 410

16. Example: Coincident Selection
If Address is 1001:
A3, A2 = 10, row decoder line 2 active
Activating RAM 8,9,10 & 11
A1, A0 = 01, column decoder line 1 active
Activating RAM 1,5,9,13
The intersect RAM is RAM 9 is activated. Other RAM cells not selected are disabled.
Then it depends on the operation functions (Read or Write)
Read : Data out thru OR gate and tri-state buffer
Write : Data available on the Data input line is transferred into the selected RAM cell.
Figure : 9.7
Morris Mano, pg 410

17. Constructing RAM
Previously : Block Diagram of a 16 X 1 RAM using 4 X 4 RAM Cell Array
How to create 8 X 2 RAM using 4 X 4 RAM Cell Array?
Number of Address bits = 8 = 23 = 3-bits
Number of Data bits = 2-bits

18. 3-bits addressing
2-bits at Row Decoder
1-bit at Column Decoder
Since 2 bits at a time are to be written or read:
2 input lines
Data input 0
Data input 1
2 output lines
Data output 0
Data output 1
Example:
If Address is = 011
Row Decoder = line 1
RAM = 4,5,6 & 7
Column Decoder = line 1
RAM = 2,6,10,14 and
3,7,11,15
Therefore : Cell 6 & 7 are activated
Figure 9.8 : Morris Mano, pg 411

19. Constructing RAM How about 32K X 8 bit? Address bit = 32 x 210
= 25 x 210= 15-bits
Data bit = 8-bit
Without Coincident selection a single decoder would have 15 inputs and 32,768 outputs. (32 x 1K = 32 x 1024)
And 32,800 no of gates.
With Coincident selection:
Make row and column equal
Total RAM = 32K x 8 = 256K =
Take Sq Root of = 512
512 = 29 , meaning 9-bits is fed to the ROW Decoder.
Remaining 6-bits is fed to the COLUMN Decoder.
Row Decoder = 9 to 512 line decoder
Column Decoder = 6 to 64 line decoder
No of gates = 608

20. ARRAY of SRAM ICs
If an application is larger than the capacity of one chip, then
There is a need to combine a number of chips in an array to form a required size of memory.
Depends on 2 parameters
No of words
No of bits per word
Number of words = address line
1-bit added to address bit would double the no of words
Number of bit = data input & output
1-bit added to the word size, 1 data input & output must be added

21. Example : memory Chip.
How to construct a 256K X 8 RAM using this 64K X 8 RAM Chip?
No of words is the same
No of address is not the same (64K  256K)
64K = 26 x 210 = 16-bit address bit
256 = 28 x 210 = 18-bit address bit
An additional 2 bit is needed for the address bit

22. Constructing 256K X 8 RAM using four 64K x 8 RAM Chip
2 additional address bit is applied to a 2 x 4 decoder and represent the MSB of the address bit.
How many 64K x 8 RAM chip to add?
Additional 2 bit = 22 = 4 of 64 x 8 RAM
Use Memory Enable to activate the decoder.

23. Constructing 256K X 8 RAM using 64K x 8 RAM Chip
When bit 17 and 16 = 00
The first 64 x 8 RAM is activated
Address : 0 – 65,535
When bit 17 and 16 = 01
The 2nd 64 x 8 RAM is activated
Address : 65,536 – 131,071
When bit 17 and 16 = 10
The 3rd 64 x 8 RAM is activated
Address : 131,071 – 196,607
When bit 17 and 16 = 11
The 4th 64 x 8 RAM is activated
Address : 196,608 – 262,143
Figure 9.10: Morris Mano, pg 413

24. What is we are to expand the word size?
Example : 64K X 16 using 64K X 8 chip
No of chip to be use refers to the word size.
In this case, 16-bit is to be constructed from
8-bit words
Therefore 2 of 64K X 8 Chip is to be use
Connections:
Address line is input to both chips
CS is common to both chips
R/W control input is also common to both chips
INPUT & OUTPUT DATA LINE is SPLIT

25. Constructing a 64K X 16 using 64K X 8 chip
Din [15..8]
Din [7..0]
Dout [15..8]
Dout [7..0]

26. Exercise
How many 128K x 16 RAM chips are needed to provide a memory capacity of 1 M bytes?
How many bits of address lines are required to access 1M bytes? How many of these lines are connected to the address inputs of all chips?
How many lines must be decoded to produce the chip select inputs? Specify the size of the decoder.

27. THANK YOU