Ethernet Bomber Ethernet Packet Generator for network analysis Final Presentation Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008

Project Goals Developing a hardware Ethernet packet generator for Ethernet networks benchmarking. Support stand-alone operation with several user configurations. Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA.

Project Goals Learning common communication protocols such as Ethernet, UDP, IP Learning HW development language and tools. Building SW application to support and control the HW design.

Architecture guideline: Hardware Optimization: - Accelerating the NIOS by implement large instruction/ data cache. - Using high speed external memory – DDR2 - Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Increasing core clock from 100MHz to 166.67MHz using only one PLL.

Architecture guideline: Software Optimization: - Using the UDP protocol (instead of TCP) to increase throughput performance - Networking with InterNiche’s “NicheStack” fully configurable networking stack and MicroC/OS-II operating system. - Raising compiler optimization level to maximum (3).

UDP/IP Packet generator Block Diagram NIOS II terminal JTAG JTAG Debug Module PHY Marvell MII Ethernet MAC Altera TSE On chip Memory RJ-45 SGDMA Interface UDP/IP Packet generator External Ethernet 10/100 Mbps NicheStack UDP Networking Nios II DDR2 HP Controller + PLL @ 333MHz Ext. CLK 100MHz Flash HP Controller DDR2 SDRAM Flash memory

SOPC Architecture DDR2 Memory Controller JTAG UART On-chip Memory NiosII Processor JTAG Debug Module Data M Inst S System Timer S S Avalon Main BUS (HS) Pipeline Bridge (LS) Avalon Tristate S M SGDMA TX S Src SGDMA RX S Sink Simple I/O Controllers S FLASH Memory Controller S Triple speed Ethernet MAC Sink Src S

SOPC Architecture

Software Design Overview The application code is based on a template supplied by Altera for networking application designs (Simple Socket Server template). The TSE device driver is also supplied by Altera and needs to be integrated to the software build in Nios II EDS library configuration. Both the IP layer and the device driver are supplied by InterNiche Technologies. Using third party WireShark 1.2.5 Network Protocol Analyzer (freeware) at the receiver station.

Software Structure – Thread Level Benchmarking Application Task NicheStack Tasks benchmark_initial_task() Priority 1 Program main() tk_netmain() Priority 2 tk_nettick() Priority 3 benchmark_driver() Priority 4 Lower number = Higher priority

Software Structure – Code Level benchmark_initial_task() main() nios_get_command_string() bmcommand_from_console() print_result() benchmark() print_test() bmprint_start() benchmark_driver() netmain() alt_iniche_init() iniche_net_ready YES NO legal command? Calling Flow udp_sender_plain() udp_sender() socket() sendto() Delay? gettimeofday() waiting done? Sending done? bmprint_menu()

System Setup

Benchmarking Example - Transmitter

Benchmarking Example - Receiver

Benchmarking Example - Results

Benchmarking Example - Results

Benchmarking Example - Results

Benchmarking Example - Results

Conclusion Networking Performance As published by Altera and InterNiche, reaching maximum link speed using this integrated design is doable, without the need of implementing the IP layer in HW. Altera design suit and documentation Although Altera’s documentation resources are almost endless, more than once we encountered mismatch between several documents (Quartus/NIOS/SOPC) Future designs on this hardware platform Our hardware platform consists of all the required features for future fast networking standalone designs