1. KM3NeT Offshore Readout System On Chip A highly integrated system using FPGA COTS S. Anvar, H. Le Provost, F. Louis, B.Vallage – CEA Saclay IRFU – Amsterdam/NIKHEF, 2008 September 9

2. KM3Net “Readout System On Chip” (RSOC) Assumptions –Off-Shore Ethernet network topology –An Ethernet node is located near a set of Optical Modules Principles –ANTARES-like design with much higher level of integration Reduce power & space requirement Reduce cost –Flexible Can be tuned to a specific detector configuration (number of OMs per node, data rates…)

3. RTOS Memory SDRAM (64 MB) Memory Flash (4 MB) Processor boot The ANTARES Off-Shore Processor Board Processor (Motorola MPC860P@80MHz) Slow Control Slow Control Task Slow-Control for the Storey 100Mb/s Ethernet Link To shore station Data Task Data Data from storey (ASIC to digitalise) Programmable Logic Programmable Logic FPGA (1000k gates) Readout System On Chip : One Component

4. The KM3Net Off-Shore Processor Board XILINX VIRTEX4-FX Processor IBM PPC405 @450 MHz Serial Ethernet CPU Bus Arbiter Custom Logic To Shore Station ST LCM Slow Control Bus Front End ASICS LVDS Links OM 0 OM 1 OM 2 ST : Slow control Transceiver OM : Optical Module LCM : Local Control Module DDR Memory Flash Memory Small Logic Configuration Port

5. A KM3Net RSOC demonstrator Upgrade of the ANTARES Offshore DAQ Hardware-Firmware-Software Demonstrates the performances in realistic conditions on a ANTARES LCM test bench –Evaluate the network throughput versus operating frequency –Evaluate the power

6. Upgrade of the ANTARES Offshore DAQ Software –VxWorks 6.3 Board Support Package for the Xilinx ML405 board available. Bootrom and vxWorks image are running. –The Offshore “foooDaq” software have been fully modified and recompiled for the PPC405 processor Firmware –The master/slave interfaces have been modified to support the PPC405 instead of the MPC860 processor. –The LVDS drivers are mapped in the Xilinx device. –The whole design (6 ASICS links) “Readout SOC” have been synthesised/placed/routed -> XC4VFX40-10 80% area occupancy PPC405@300MHz, Processor Bus@100MHz –VHDL code Fully simulated

7. RSOC Design Test Setup (1) ANTARES LCM Crate Pseudo-Clock Board 3 ARS Boards CPU Slot OM 0 OM 1 OM 2 Adaptation Board XILINX ML405 Board XC4FX20 device (PPC405@300MHz, 1 Gb/s Ethernet link) 128 MB DDR SDRAM 8 MB Flash Will be upgraded with a ML507/XC5FX70 (board fully compatible) + experiment clock integration (virtex5 feature) ANTARES Run Control

8. RSOC Design Test Setup (2) ML405 Kit Adaptation boards LCM crate ARS board

9. RSOC test status - What is running (fully tested) –The slave interface (PPC405->custom logic) –Run Control/DAQ Harness –Framing/interrupts –ARS slow control To debug for a fully RSOC –ARS data path (firmware) –Some random crash@start (software)

10. Readout System On Chip / Phase 2 Developments are based on PRISM component -Virtex 4FX60 -256 MB DDR2 SDRAM -128 MB Flash -10/100/100 Base T Ethernet -160 GPIOs

11. KOALA Board (KM3Net Optical module Acquisition board for LocAl Processing) prototype board PRISM VIRTEX4-FX Processor module Serial Ethernet gigabit link Scott OM 0 Scott OM 1 Scott OM 2 Power supply Dc/Dc 400V OM 0 Base power supply Instrumentation Compass Tiltmeter Humidity Etc… OM 1 Base power supply OM 2 Base power supply

12. KOALA located in an OM KOALA board PMT base

13. Scott test bench -Virtex 4FX60 development board with vxWorks -Daughter board with Scott and associated circuits -Possibility to read PMT analog signal -Make use of KM3Net software study (S.Anvar, F.Chateau)

14. NovemberFebruary 20082009 September KOALA Scott Test bench ASIC Scott Development Submission Operational Manufacturing Development Operational June Development plan Development Manufacturing RSOC Ready for use Evolution/Prism & Scott

15. Conclusion RSOC upgrade of the ANTARES offshore DAQ in the debugging phase. SCOTT test bench based on RSOC Hardware and Software KOALA board development for a common SCOTT/RSOC demonstrator Pre-study foreseen for the Integration of the clock distribution to the RSOC.

16. Virtex-4 FX Network Throughput Maximum achievable TCP sending throughput PPC405@300MHz, Processor Bus@100MHz, on chip Gigabit Ethernet MAC (TEMAC) –MontaVista Linux : 520 Mb/s, Application Note Xilinx xapp1023. –WindRiver vxWorks : 590 Mb/s, Application Note Xilinx xapp941.

17. Conclusion RSOC upgrade of the ANTARES offshore DAQ on its way. No blocking point. ~3 Months to finalize it and give relevant inputs for the Technical Design Report. Digital solutions, hardware and software, off-the-shelf Integration of the clock distribution to the RSOC under study.