Network On Chip Platform FINAL PRESENTATION - SPRING 2009 - Instructor: Yaniv Ben-Itzhak Students: Ofir Shimon Guy Assedou Spring 2009

General Concept NoC - Network On Chip A network-like structure composed of inter-connected modules which exchange data efficiently and in very fast rates Spring 2009

NoC Platform – Project Definition Design and build basic NoC CPU Module as a part of multi-core NoC platform on an FPGA, and implement a tailored HW/SW verification system. Spring 2009

NOC Platform Architecture ADAPTOR (cpu-router) NIOS II softcore ROUTER (router-memory) MEMORY CONTROLLER Spring 2009

CPU Module Architecture ADAPTOR (cpu-router) NIOS II softcore ROUTER MEMORY CONTROLLER CPU Module Architecture System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface packets controls NIOS II softcore Spring 2009

System Configuration Nios II soft-core System Interconnect Fabric CPU freq – 100 MHz Pipeline Increase throughput for peripherals that require several cycles to return data Two phase pipeline – Address & Data Only Read requests can be pipelined System Interconnect Fabric Selected Bus Interface - Avalon Memory Mapped: Used for R/W interfaces on master and slave components in a memory-mapped system Spring 2009

System Configuration Router System Virtual channels - One channel was defined for both R/W operations in order to keep static routing in the platform. Flit type - Head & tail - easy to implement System Clock frequency – 100 MHz Max Packets per CPU Module – 16 Packet size – 77 bits Spring 2009

Packet Packet Structure Packet Header Flit Service Level Packet Type Flit Header Data Service Level Packet Type Processor ID Request Type Data Address Memory X Coordinate Y 76 75 74 73 72 71 70 39 38 8 7 4 3 0 Spring 2009

Adaptor Architecture BUFFER IN (FIFO) ROUTER_TX CREDITS CALCULATOR System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface packets controls NIOS II softcore Adaptor Architecture BUFFER IN (FIFO) ROUTER_TX flit data address waitrequest packet control BUS_TX CREDITS CALCULATOR control control Spring 2009

Verification & Validation Behavioral Simulations Pre-synthesis VHDL for logic functionality with ModelSim Develop Verification Environment Full System Testing Create high load of memory accesses in system Spring 2009

Verification System Architecture LOOPER packets controls CPU Module TESTER System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface NIOS II softcore Spring 2009

Behavioral Simulations - Write Waveforms   Screen clipping taken: 29/06/2009, 12:22 Behavioral Simulations - Write Waveforms Spring 2009

Behavioral Simulations - Read Waveforms   Screen clipping taken: 29/06/2009, 12:22 Behavioral Simulations - Read Waveforms Spring 2009

LOOPER Module Architecture packets controls CPU Module TESTER System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Nios II LOOPER Module Architecture BUFFER IN (FIFO) packet control ROUTER_TX CREDITS CALCULATOR packet packet Spring 2009

Verification Software Harsh and intensive environment that will test the hardware Write/Read randomly to memory Increased paced in compare to average memory access rate Spring 2009

Verification Software - Pseudo-Code Randomize number of write instructions to issue -> wr Iterate wr times Write data to memory Store data & address in dedicated arrays for later use Increase address & data value Randomize number of read instructions to issue -> rd Iterate rd tims Read data from memory Compare data from memory with data stored in data array Update statistics Spring 2009

Test Results Program Iteration Example: Final Results: Spring 2009

FPGA Resources Usage Spring 2009

Development Tools Hardware: Software: GIDEL ProcStar II 180 Board Stratix II 60 FPGA PC Software: Quartus II SOPC Builder NIOS II IDE ModelSim GIDEL PROCWizard Spring 2009

Project Milestones Spring 2009 Characterization Report & Presentation Tutorials VHDL Nios II softcore – “hello world” System Interconnect Fabric Tools Ramp-up Quartus II SOPC Builder HDL Designer NIOS II IDE Router Ramp-up Mid-semester presentation Implementing CPU-ROUTER Adaptor Implementing CPU Module Implementing LOOPER H/W System Integration S/W Coding Final Presentation Spring 2009

Achievements & Further Work Main Project Achievements Fully operational NOC based system in hardware (FPGA) Modular CPU Module - building block which enables easy scalability of future NOC platforms Verification & Validation environment (HW & SW) Further Work Complete Memory Module Implementation Complete Platform integration In-depth Platform analysis Spring 2009

Thank you! Spring 2009

Adaptor interconnections System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface packets controls NIOS II softcore Adaptor interconnections Router Virtual channels can be modified as required. 2 channels were defined. One for Read requests and one for Write requests. Flit type Three types – head, tail & head and tail Only head & tail - easy to implement שקופית גיבוי Spring 2008

Adaptor interconnections System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface packets controls NIOS II softcore Adaptor interconnections System Interconnect Fabric - Bus Available interfaces to SIF Clock Interface Interrupt Interface Avalon Memory-Mapped Tristate Interface Avalon Streaming Interface Conduit Interface Avalon Memory-Mapped Interfaces Interface to Bus is Avalon Memory Mapped Used for R/W interfaces on master and slave components in a memory-mapped system שקופית גיבוי Tristate- מאפשר תקשורת עם רכיבים שיושבים מחוץ ל FPGAץ מעט פינים הרבה רכיבים Streaming מאפשר תקשורת חד כיוונית בקצבים גבוהים מאוד למשל DSP Conduit מוליך מספר סיגנלים לטופ לוול Spring 2008

Adaptor interconnections System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR Avalon MM Interface packets controls NIOS II softcore Adaptor interconnections Slave Transfers: Typical Slave Read and Write Transfer Burst Transfer Pipelined Transfer Pipeline Increase throughput for peripherals that require several cycles to return data Two phase pipeline – Address & Data Only Read requests can be pipelined שקופית גיבוי Burst-כתובת התחלתית ואופסט למשל מערך לכל חבילה לייטנסי שונה Variable Latency Spring 2008

Nios II Sofcore Processor שקופית גיבוי Spring 2009