1. NETWORK ON CHIP ROUTER Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter Final presentation part A Winter 2006

2.  NoC concept  Design architecture  Architecture logic implementation  Design simulation  What’s left to do... Agenda

4. Problem: Power, size and performance not practical for multi-processor chips using a single bus interconnection. Solution: Network on Chip, based interconnection: fast, reliable data and low power consumption.

5.  Implement a router for NoC in VHDL based upon research made by faculty members.  Design and implement interface unit between NoC routers and process units.  Design and implement an application of multi processing units using a Network on Chip based interconnection. Project Goals

6. Network Schematic Processing Unit NoC ROUTER Interface

7. Network problems  Transmitting large data (buffer size, latency)  Loss of data due to full buffer  Data priority  Data from several inputs to one output  Blocked path prevents data transmission

8. Data in network  Packet based data flow  Single-flit or multi-flit packets (wormhole)  Service level support (packet priority)  Virtual channel support (router feature)

9. Packets in Wormhole architecture Packet bodyTarget Address Command A whole Packet  Each Packet is divided to Several smaller segments (flits)  Each flit is several bit width

10. Interface Process Unit Process Unit Process Unit Process Unit Process Unit Processing Unit Interface Between Bus & Router Packets in Wormhole architecture From Bus to Packets To Router Local Bus “network language” “unknown language”

12. Router 5x5 Processing Unit Data Control Data Control ROUTER Crossbar Input port West East South North Processing Unit Interface Module output port next router

13. Flit structure one flit Type Service Level Data out x 2bit x 12bit Or 8bit – first flit of packet CRT (first flit of packet) x 4bit (network size factor) Lsb bit Msb bit

14. 4 msb bits of every flit Service Level (SL) : Block Transfer = “00” (unimplemented yet) Real-Time = “01” (unimplemented yet) RD/WR = “10” (implemented as SL2) Signaling = “11” (implemented as SL1) Data Type : Idle = “00” – no signal Body = “01” – middle/header flit of a packet EP = “10” – end of packet FP = “11” – full packet (single flit packet)

15. Router design architecture guidelines  Input port serves as register-buffer  Crossbar designed in a full-connectivity (all inputs to all output)  Output port recognizes data waiting in input port buffer to be delivered, and extracts it (read command from output port goes to one or more inputs)

16. Routing Control & Terminology  Each Service Level (SL) has an independent path from input port until output port buffer  According to Current Routing Table (CRT) data is channeled to the appropriate output port, via the crossbar  In each output port the Current Serviced Input Port (CSIP) is determined by a Round-Robin logic which arbitrates between input ports waiting for transmission  Next Buffer’s State (NBS) determines if next router is ready to receive data

17. Router Input Port FIFO ROUTER InputPort CRT Switching SL Data In flits PREVIOUS ROUTER IN PATH / PROCESSING UNIT Buffer credits read/write Control Crossbar Data Per Service- Level Current Routing Table SL Read lines From output- ports

18. To Output Port From Input Port Routing DATA according to CRT From Input Port To Output port Crossbar Example for 2 Service Levels DATA + CRT DATA DATA + CRT CSIP SL1 SL2 SL1 SL2 CRT

19. Router Output Port ROUTER OutputPort CSIP Buffer credits NBS CSIP NBS CSIP Buffer credits Round-Robin & control NEXT ROUTER IN PATH / PROCESSING UNIT Data In flits Switching SL Crossbar Currently Serviced Input Port Next Buffer State Data Per Service- Level Read lines To input- ports

20. Part A Final Goal  3x3 Router  2 Service Levels  Receiving/Transmitting A One Flit Packet (FP)

22. Final Router Design Part A  Modular 5x5 Router, 16 bit data width  2 Service Levels (SL1, SL2)  Receiving/Transmitting Multi-flit packets (not only FP*) * FP = Full-Packets

23. Top view : Input port output port crossbar

24. Cross-Bar (top view):

25. Cross-Bar : Data from Input CRT direction Data to output CSIP Data ready (input for Round Robin)

26. Ports : output port Input port

27. Input-Port (top-view) Data in from previous router/module To crossbar

28. Input -P ort : Route to SL path FIFO + CRT read/write control

29. Output -P ort (top-view) Data out to next router/module From crossbar

30. Output -P ort (per SL): NBS Round Robin

32. Design Simulations : 1.Cross-Transmit 2.Buffer Credits 3.Round-Robin 4.Service-Level 5.Heavy Traffic

33. 1. Cross-Transmit : 3 cycles delay Two Packets from different inputs to different outputs simultaneously

34. 2. Buffer Credits : Filling NBS Emptying NBS 1 cycle delay No transmission from output port if the next input port is full Output port controls the function

35. 3. Round-Robin : Arbitraging between input port at the same SL In a round form (round-robin) Each flit is full packet When receiving flits from different inputs to the same output simultaneously, each flit is transmitted in turn

36. Not each flit is full packet BODY EP Arbitraging between input port at the same SL In a round form (round-robin) FP 3. Round-Robin : Same as before, but with multi-flit packets

37. SL2 for 250 ns (5 clock cycles) 1 cycle of SL1 2 cycle of SL2 1 cycle of SL1 3 cycles delay from input) 3 cycle of SL2 4. Service-Level : Higher priority packet halts transmission of a lower priority packet

38. 5. Heavy Traffic : receiving & transmitting simultaneously different SL, from and to different input & outputs SL1 then SL2 SL2 SL1 then SL2 SL1 Round-Robin of SL2Round-Robin of SL1 Halt of SL2 for SL1

39. Simulation conclusions :  Latency = 3 clock cycles for a flit  Throughput = outputs 1 flit on each clock cycle (no wasted cycles)  No latency in output transition when between SL or in switching between inputs  Router can handle receiving & transmitting of multi-flit packets of different SL, from and to different inputs & outputs simultaneously

40. CRT FIFO Adding Virtual Channel ROUTER InputPort Control routing by CRT Buffer credits Input Port Control Crossbar Data Per Service- Level CRT Switching SL Input Buffer PREVIOUS ROUTER IN PATH / PROCESSING UNIT Read command from output

41. Adding Virtual Channel – not as simple as it sounds PROBLEM: Multi flit packets might split to different virtual channels and may be confused as other packets

42. Development of interface Process Unit Process Unit Process Unit Process Unit Process Unit PPC Interface Packets in Wormhole architecture To Router PLBorFSL User-logic translating data from address to flits in SL with appropriate CRT IPIF

43. Second Semester Goals  Adding Virtual-Channel to Router architecture  Development of interface to the network  Final project goal : Implement a QNoC based application on a FPGA for validation of NoC.

44. Project schedule - Achieving Final Goals  Implement Router On Virtex II Pro  Validating & Extracting design parameters (area, timing) – 3 weeks  Add virtual channel to existing router – 3 weeks  Ramp up understanding of PPC architecture or Micro-Blaze for connecting user-logic in order to build a QNoC based application on the Virtex II Pro – 2 weeks  Design, implement & simulate interface – 4 weeks  Implement a QNoC based application on a FPGA for validation of NoC – 3 weeks