1. 1 Multi - Core fast Communication for SoPC Multi - Core fast Communication for SoPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Performed by: Moshe Bino Alex Tikh Supervisor: Evgeny Fiksman Spring 2008

2. 2 Single processor vs. multi-core Single core is reaching its performance limits:  Dynamic power consumption rises linearly with freq’  Heat dissipation ‘Power wall’ solution is keeping the frequency, while rising the number of transistors. Natural solution is Parallel computing Multi-Core efficiency depends on fast comm` between cores and network topology.

3. 3 Fast communication Major inter-communication techniques:  Shared memory  Hardware memory synchronously accessed by multiple processors to provide inter-communication through data sharing.  Remote procedure calls  Inter-processors communication technology that allows one processor to cause a subroutine or a procedure to execute in another processor’s address space.  Message passing interface (MPI)  Programmable interface for advanced data passing

4. 4 Network topologies - pros & cons Point to point (PTP) High speed x Bad scalability Bus Simple to implement x Low throughput Star Easily expendable network x Performance & scalability depend on hub capabilities Mesh - NoC Easy to expend the system efficiently x Difficult to troubleshoot

5. 5 Chosen topology Mesh topology NoC Routing nodes Leaf processor’s cores MPI logically defines clusters Comm - cluster Rank - member Cores amount is limited only by chip resources NoC is the best choice for network topology

6. 6 System architecture Router node Project examines FPGA chips category Main core connected to I/O Multi - clock domain

7. 7 Logic design – Router node Time limited Round Robin arbiter. Port to Port & broadcasting Modular design Two main units: 1.Permission Unit 2.Port FSM

8. 8 Software Layers Application MPI functions interface Network hardware independent implementation Data relies on message structure Physical designed for FSL bus Design modularity in hardware and software

9. 9 Software Synchronization Parallelism: Several messages traverse in the system simultaneously Keep network clean: Processor forced to receive incoming message Ease network load: Maintenance: False/error messages dismissed locally by software Synchronization: Each processor DB synchronized locally by software

10. 10 System development – Project workflow Hardware Test and Simulate Software Test and Simulate Hardware – Simulation environment Message generator Software – Development environment Timing

11. 11 System verification & integration Hardware Test and Simulate Software Test and Simulate Software & Hardware Debug & Synth & PAR Send messages with different lengths Measure time - statistics Scalable application to measure network efficiency/ performance Optimization Performance App.

12. 12 Summary Multi core solution for single core problem Energy consumption Heat dissipation NoC is the best choice for network topology Scalability - Area Performance - frequency Design modularity in hardware and software Easy to expend the system efficiently NoC implementation adjusted for FPGA platform Minimal lines and logic units Synchronous system Complete HW & SW solution for Multi-core Comm. system

13. 13 References [1] I.Cidon & I.Keidar: Zooming in on Network on Chip Architectures. [2] E.Bolotin: NoC clubnet presentation.