Computer Organization CS224 Fall 2012 Lesson 22

The Big Picture  The Five Classic Components of a Computer  Chapter 4 Topic: Processor Design Control Datapath Memory Processor Input Output

Introduction  CPU performance factors l Instruction count -Determined by ISA and compiler l CPI and Cycle time -Determined by CPU hardware  We will examine two MIPS implementations l A simplified version l A more realistic pipelined version  Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, ori, slt Control transfer: beq, j §4.1 Introduction

The Performance Perspective  Performance of a machine is determined by: l Instruction count l Clock cycle time l Clock cycles per instruction  Processor design (datapath and control) will determine: l Clock cycle time--CCT l Clock cycles per instruction--CPI  This week: Single cycle processor (datapath + control) l Advantage: One clock cycle per instruction l Disadvantage: long cycle time CPI Inst. CountCycle Time

Processor Design Steps 1. Analyze instruction set => datapath requirements l the meaning of each instruction is given by the register transfers (ISA model => RTL model) l datapath must include storage element for ISA registers -possibly more l datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the RTL requirements

Processor Design (cont’d) 4. Analyze implementation of each instruction to determine setting of control points that effect the register transfer. 5. Assemble the control logic 6. RTL datapath and control design are refined to track physical design and functional validation l Changes made for timing and errata (a.k.a. “bug”) fixes l Amount of work varies with capabilities of CAD tools and degree of optimization for cost/performance

Subset of Instructions  To simplify our study of processor design, we will focus on a subset of the MIPS instructions Memory: lw and sw Arithmetic: add, sub, and, ori, and slt Branch: beq and j  Example in lecture uses ori rather than or covered in text, to demonstrate one more category of instructions  The method of implementing other instructions should come naturally from these

MIPS Format Review  R-Format l add rd, rs, rt l sub rd, rs, rt OP=0rs rt rdsafunct Bits first source register second source register result register shift amount function code

MIPS Format Review (cont)  I-Format l lw rt, rs, imm l sw rt, rs, imm l beq rs, rt, imm l ori rt, rs, imm  Reminders l Branch uses PC Relative addressing (PC × imm) OPrs rt imm Bits65516 first source register second source register immediate

MIPS Format Review (cont)  J-Format l j target  Reminders l Uses pseudodirect addressing (target × 4) to allow addressing 2 28 bits directly l Uses top 4 bits from PC OPtarget Bits626 jump target address

Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

What Happens?  It’s hard to see how we should go about organizing the processor  To start thinking about it, look at what happens on each instruction l The instruction specified by the PC is fetched from memory One or two registers are read ( lw vs. add for instance) l The ALU must be used to add, subtract, etc. l The results are stored (to memory or a register)

Instruction Execution  PC  instruction memory, fetch instruction  Register numbers  register file, read registers  Depending on instruction class l Use ALU to calculate -Arithmetic result -Memory address for load/store -Branch target address l Access data memory for load/store l PC  target address or PC + 4

Processor Overview Data flows through memory and functional units

Multiplexers Can’t just join wires together Use multiplexers

Control

Logic Design Basics §4.2 Logic Design Conventions  Information encoded in binary l Low voltage = 0, High voltage = 1 l One wire per bit l Multi-bit data encoded on multi-wire buses  Combinational element l Operate on data l Output is a function of input l Example: ALU  State (sequential) elements l Store information or state l Example: Register File

1-bit Full Adder 1 bit ALU  Using a MUX we can add the AND, OR, and adder operations into a single ALU A B Cout Cin ALUOp Mux Result

4 bit ALU A0 B0 1-bit ALU Result0 CIn0 COut0 A1 B1 1-bit ALU Result1 CIn1 COut1 A2 B2 1-bit ALU Result2 CIn2 COut2 A3 B3 1-bit ALU Result3 CIn3 COut3 ALUop 4 4 A B ALUop 3

Combinational Elements 32 A B Sum Carry Adder Carry_In 32 A B Y Select MUX 32 A B Result Zero OP ALU Adder ALU MUX 32

D Latches  Modified SR Latch  Latches value when C is asserted C D Q Q

D Flip Flop  Uses Master/Slave D Latches D CLK Q Q D Latch D C Q Q D Latch D C Q Q

Storage Element: Register  Register l Similar to D Flip Flop -N bit input and output -Write Enable input l Write Enable -0: Data Out will not change -1: Data Out will become Data In l Data changes only on falling edge! Clk Data In Write Enable NN Data Out

Storage Element: Reg File  Register File consists of 32 registers l Two 32 bit output busses -busA and busB l One 32 bit input bus -busW l Register 0 hard wired to value 0 l Register selected by -RA selects register to put on busA -RB selects register to put on busB -RW selects register to be written via busW when Write Enable is 1 l Clock input (CLK) -CLK input is a factor only for write operation -During read, behaves as combinational logic block –RA or RB stable  busA or busB valid after “access time” –Minor simplification of reality Clk busW Write Enable 32 busA 32 busB 555 RWRARB bit Registers

Storage Element: Memory  Memory l One input bus: Data In l One output bus: Data Out l Address selection -Address selects the word to put on Data Out -To write to address, set Write Enable to 1 l Clock input (CLK) -CLK input is a factor only for write operation -During read, behaves as combinational logic block –Valid Address  Data Out valid after “access time” –Minor simplification of reality Clk Data In Write Enable 32 Data Out Address

Some Logic Design…  All storage elements have same clock l Edge-triggered clocking l “Instantaneous” state change (simplification!) l Timing always work if the clock is slow enough Cycle Time = Clk-to-Q + Longest Delay + Setup + Clock Skew Clk Don’t Care SetupHold SetupHold