1. Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath

2. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Topics Construct the “Datapath” & “Control unit” for MIPS instruction set Design implementation for core MIPS – Memory reference (Load/Store) instructions – Arithmetic/logical instructions – Branch instructions

3. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 3 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Introduction The 5 classic components of a computer Control Datapath Memory Processor Input Output

4. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 4 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Consists of: – Datapath – Control Responsible for: – Using program counter (PC) for instruction address – Get the instruction from memory – Read registers – Use the instruction to decide exactly what to do The Processor

5. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 5 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Actions needed complete an instruction depend on the class – Memory reference: Access memory to write / read data – Arithmetic: Write data from ALU back into registers – Branch: Change next instruction address The Processor

6. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 6 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) For all instructions the first 2 steps are identical – Fetch memory contents to which PC points – Read registers specified in instruction All instructions use the ALU after reading the registers – Memory-reference For address calculation – Arithmetic For operation execution – Control flow (branch) For comparison The Processor

7. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 7 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath The component of the CPU that performs arithmetic operations Main components – Instruction & data memories – Register files – Program Counter (PC) – ALU – Adders – Others...

8. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 8 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Control Select operations Controls data flow Synchronized by the clock Consists mainly of combinational circuits – Gates – MUX’s

9. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 9 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Performance Perspective Performance of a machine (or a program) is determined by: – Instruction count – Clock cycle time – Clock cycles per instruction (CPI) Compiler & ISA determine instruction count Datapath & Control determine clock cycle time & CPI CPI Inst. Count Cycle Time Compiler & ISA Datapath & Control

10. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 10 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Performance Perspective Single cycle processor – Advantage: One clock cycle per instruction – Disadvantage: Long cycle time Multiple cycle processor – Advantage: Short cycle time – Disadvantage: Multiple clock cycles per instruction

11. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 11 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Design- What will be included? Subset of core MIPS instructions – Memory reference(R-Format ) Load/Store instructions lw, sw – Arithmetic/logical (R-Format) add, sub, and, or, slt, ori – Branch (I- & J-Formats) beq, j

12. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 12 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath Design What will not be included? – Multiplication & division instructions – Floating-point instructions Design guidelines: – Make common case faster – Simplicity favors regularity

13. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 13 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Abstract View – PC supplies instructions to “Instruction Memory” – Registers hold operands – ALU computes results – Results stored in data memory or values fetched from data memory into registers Datapath Design Data Memory Register File Instruction Memory PC ALU Data Register# Instruction Address Register# Address Data

14. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 14 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Functional units required: – Combinational: Elements that operate on data values Output depends on current input ALU Other components – Sequential: Elements that contain state Instruction memory Data memory Registers Datapath Design

15. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 15 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: State Element Element has internal storage (Memory) – D-Flip-flop – Memories – Registers Element Has at least – Two inputs Data to be written into element Clock to determine when data is written – One output Data value written in earlier clock cycle

16. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 16 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: Clocking methodology Defines when signals can be read / written – Prevents unpredictability in reading or writing Un-clocked: – Used in asynchronous logic – Values updated as soon as input arrives Clocked: – Used in synchronous logic – Values updated with clock input, anytime during which the clock is asserted Edge-triggered: – Values updated only on clock edge (rising or falling edge, depending on the logic used) We will assume an edge-triggered methodology

17. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 17 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Input: – Values written in a previous clock cycle Output: – Values to be used in the following clock cycle Prevents reading the signal in the same time it is written More than one action can take place in the same clock cycle cycle time rising edge falling edge Review: Edge-triggered methodology

18. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 18 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: Timing Methodology Clock cycle(Tick/Period): – Time for one clock period, usually of the processor, which runs at a constant rate Access time: – Time between the initiation of a read request and when the desired word arrives Cycle time: – Minimum time between requests to memory – Cycle time should be greater than access time to keep address line stable between accesses

19. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 19 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: Timing Methodology Typical execution cycle: – Read contents of some state elements, – Send values through some combinational logic – Write results to one or more state elements – Clock period should cover all these activities Clock Cycle t propagation t setup t combinational State Element 2 Clock at time t Clock at time t+  State Element 1 Combinational Logic Write control

20. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 20 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: Timing Methodology Total clock period = t prop + t comb + t setup + t skew – t prop : Propagation time in first state element – t comb : Propagate time in the combinational logic – t setup : Time needed to reach the steady state to apply to the second state element – t skew : Time to compensate for the different paths taken to let the clock edge reach all state elements A state can only be changed if the write control signal is asserted and the clock edge occurs

21. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 21 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Required Datapath Components is t e r R e ad data 1 R e ad data 2 Data Data Reg i ste r numbe r s RegWrite Register file R e g s W r i t e r e g is t e r R e ad r e g is t e r 1 R e ad r e g is t e r 2 W r i t e data 5 5 5 AL U result AL U Ze r o ALU c ont r ol ALU 3 I ns tr uct i on memo r y I nst r uction add r es s I n s t r uction Instruction memory PC Program counter Add Sum Adder 1632 Sign ex t end Sign extension MemRe a d M em W r it e Data memo r y R ead da t a Data memory unit Wr it e d ata Address

22. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 22 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Required Datapath Components Memory units(Instruction & Data memory): – State element units to hold & supply instructions & data Program Counter (PC): – State element unit to keep the address of instructions Adder/ALU: – Increment program counter to address of next instruction – We can build the adder from the ALU by wiring the control lines to add-operation Control signals: – ALU Control – RegWrite – MdemRead – MemWrite

23. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 23 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Contains the processor’s 32 registers Read/written by supplying register number Implemented with a decoder for each read/write port Array of registers is implemented using D-FFs Reading doesn’t change the state – Non-destructive Writing changes the state – Destructive Review: Register File

24. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 24 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) A set of 32 registers – 5-inputs 2 read-ports supply source register numbers 1 write-port supplies dest. register number 1 32-bit Data bus 1 Write enable line – 2-outputs Data from register 1 Data from register 2 – 1-Control signal Write signal No need for read signal Data is always available on the data buses. Review: Register File Register File Register Selectors Data Buses Data Bus 5 5 5 32 RegWrite Read Reg1 Write Reg1 Read Reg 2 Write Data Write Enable Read Data1 Read Data2

25. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 25 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Reading: – To read data from a register submit: Register # – For N-registers we need: n x 1 MUX Review: Register File R1 R e g is t e r 0 R e g is t e r 1 e g is t er n – Register n M u x M u x Read Data2 Read Reg1 Read Reg2 Read Data1

26. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 26 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Review: Register File Writing: – To Write data to a register, you need: Register # Data Write control signal – To choose a register Use a Decoder – Use clock to determine write C = control signal D = data lines Register number Write Register data n x 1 Decoder 0 1 n-1 n CDCD Register0 Registern Registern-1 Register1 CDCD CDCD CDCD

27. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 27 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Instruction Execution All instructions start by fetching the instruction from instruction memory Depending on instruction type, the different operands are extracted – For R-Format: op | rs | rt | rd | shamt | funct <= MEM[ PC ] – For I-Format: op | rs | rt | Imm16 <= MEM[ PC ]

28. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 28 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Instruction Execution The instruction is executed – The action depends on the type of instruction ADD:R[rd] <– R[rs] + R[rt]; PC <– PC + 4 SUB:R[rd] <– R[rs] – R[rt]; PC <– PC + 4 ORI:R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 LOAD:R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <–PC+4 STORE:MEM[R[rs]+sign_ext(Imm16)] <– R[rt]; PC <–PC+4 BEQ: if (R[rs] == R[rt]) then PC <– PC+sign_ext(Imm16)] || 00 {overflow} else PC <– PC + 4 Program counter is incremented to point at next instruction – Except for branch & jump instructions

29. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 29 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Steps 1.Analyze instruction set & determine datapath requirements 2.Select set of datapath components & establish clocking methodology 3.Assemble datapath meeting the requirements 4.Analyze implementation of each instruction to determine setting of control points that affects the register transfer 5.Assemble the control logic

30. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 30 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 1 Analyze Instruction set & datapath requirements – Memory Instruction memory Data memory – Registers (32 x 32) Read RS Read RT Write RT or RD – Increment PC – Extender to extend sign bit of immediate operand – Add and Sub register or extended immediate – Add 4 or extended immediate to PC

31. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 31 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2 Select datapath components & establish clocking methodology – Combinational Elements ALU MUX Adder – Storage Elements Register file Instruction memory Data memory – Clock Effect during reading Effect during writing

32. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 32 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2-a Combinational logic elements: – Basic building blocks: 32 A B Y Select MUX 32 A B Sum CarryOut Adder CarryIn 3232 32 B Result ALU operation ALU Zero 3 A 32

33. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 33 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2-b Storage Element: Register File – 32 registers: Two 32-bit output busses (busA &busB) One 32-bit input bus (busW) – Register is selected by: 5 selector lines to select one of the 32 registers – RA selects the register to put on busA (data) – RB selects the register to put on busB (data) – RW selects the register to be written via busW (data) when Write Enable is asserted Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 x 32-bit Register File

34. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 34 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2-b Storage Element: – Data Memory & Instruction Memory One input bus (Data In) One output bus (Data Out) Memory word is selected by: – Address to select the word to put on “Data Out” – Write Enable = 1, to allow writing data available on “Data In” bus Clk Data In Write Enable 32 Data Out Address Data/Instruction Memory

35. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 35 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2-c Clock: – Clock input is a factor only during write operation – During read operation, behaves as a combinational logic circuit: Address valid: – => Data Out valid after “access time.” Clk SetupHoldSetupHold

36. OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 36 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 2-c Assumptions: – One cycle for one instruction – Clock should allow Data transfer from register file to ALU Perform operation Put result back into ALU Clk SetupHoldSetupHold