1. Computer Organization CS224 Chapter 4 Part a The Processor Spring 2011 With thanks to M.J. Irwin, T. Fountain, D. Patterson, and J. Hennessy for some lecture slide contents

2. CS224 Spring 2011 The Big Picture The Five Classic Components of a Computer Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output

3. CS224 Spring 2011 The Performance Perspective Performance of a machine is determined by: –Instruction count –Clock cycle time –Clock cycles per instruction Processor design (datapath and control) will determine: –Clock cycle time –Clock cycles per instruction Today: Single cycle processor –Advantage: One clock cycle per instruction –Disadvantage: long cycle time CPI Inst. CountCycle Time

4. CS224 Spring 2011 Big Picture: Processor Implementation Key Ideas –Concept of datapath and control –Where the instruction and data bits go –Modern hardware organization Clocking, combinational, and sequential logic using computer organization as an example –Handling complexity Abstraction, use commonality, multilevel interpretation Approach –Start with a simple implementation and iteratively improve it

5. CS224 Spring 2011 Processor Design Steps 1. Analyze instruction set => datapath requirements –the meaning of each instruction is given by the register transfers (ISA model => RTL model) –datapath must include storage element for ISA registers possibly more –datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the RTL requirements

6. CS224 Spring 2011 Processor Design (cont’d) 4. Analyze implementation of each instruction to determine setting of control points that effect the register transfer. 5. Assemble the control logic 6. RTL datapath and control design are refined to track physical design and functional validation –Changes made for timing and errata (a.k.a. “bug”) fixes –Amount of work varies with capabilities of CAD tools and degree of optimization for cost/performance

7. CS224 Spring 2011 Subset of Instructions To simplify our study of processor design, we will focus on a subset of the MIPS instructions –Memory: lw and sw –Arithmetic: add, sub, and, ori, and slt –Branch: beq and j Example in lecture uses ori rather than or covered in text, to demonstrate one more category of instructions The method of implementing other instructions should come naturally from these

8. CS224 Spring 2011 MIPS Format Review R-Format –add rd, rs, rt –sub rd, rs, rt OP=0rs rt rdsafunct Bits655556 first source register second source register result register shift amount function code

9. CS224 Spring 2011 MIPS Format Review (cont) I-Format –lw rt, rs, imm –sw rt, rs, imm –beq rs, rt, imm –ori rt, rs, imm Reminders –Branch uses PC Relative addressing (PC + 4 + 4 × imm) OPrs rt imm Bits65516 first source register second source register immediate

10. CS224 Spring 2011 MIPS Format Review (cont) J-Format –j target Reminders –Uses pseudodirect addressing (target × 4) to allow addressing 2 28 bits directly –Uses top 4 bits from PC OPtarget Bits626 jump target address

11. CS224 Spring 2011 What Happens? It’s hard to see how we should go about organizing the processor To start thinking about it, look at what happens on each instruction –The instruction specified by the PC is fetched from memory –One or two registers are read ( lw vs. add for instance) –The ALU must be used to add, subtract, etc. –The results are stored (to memory or a register)

12. CS224 Spring 2011 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction

13. CS224 Spring 2011 Implementation Overview Data flows through memory and functional units

14. CS224 Spring 2011 Some Logic Design… Two important definitions –Combinational – output is dependent only on current inputs Example: ALU –Sequential – element contains state information Example: Registers

15. CS224 Spring 2011 1-bit Full Adder 1 bit ALU Using a MUX we can add the AND, OR, and adder operations into a single ALU A B C out C in ALUOp Mux Result

16. CS224 Spring 2011 4 bit ALU A0 B0 1-bit ALU Result0 CIn0 COut0 A1 B1 1-bit ALU Result1 CIn1 COut1 A2 B2 1-bit ALU Result2 CIn2 COut2 A3 B3 1-bit ALU Result3 CIn3 COut3 ALUop 4 4 A B ALUop 3

17. CS224 Spring 2011 Combinational Elements 32 A B Sum Carry Adder CarryIn 32 A B Y Select MUX 32 A B Result Zero OP ALU Adder ALU MUX

18. CS224 Spring 2011 D Latches Modified SR Latch Latches value when C is asserted C D Q Q

19. CS224 Spring 2011 D Flip Flops Uses Master/Slave D Latches D CLK Q Q D Latch D C Q Q D Latch D C Q Q

20. CS224 Spring 2011 Storage Element: Register Register –Similar to D Flip Flop N bit input and output Write Enable input –Write Enable 0: Data Out will not change 1: Data Out will become Data In –Data changes only on falling edge! Clk Data In Write Enable NN Data Out

21. CS224 Spring 2011 Storage Element: Reg File Register File consists of 32 registers –Two 32 bit output busses busA and busB –One 32 bit input bus busW –Register 0 hard wired to value 0 –Register selected by RA selects register to put on busA RB selects register to put on busB RW selects register to be written via busW when Write Enable is 1 –Clock input (CLK) CLK input is a factor only for write operation During read, behaves as combinational logic block –RA or RB stable  busA or busB valid after “access time” –Minor simplification of reality Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

22. CS224 Spring 2011 Storage Element: Memory Memory –One input bus: Data In –One output bus: Data Out –Address selection Address selects the word to put on Data Out To write to address, set Write Enable to 1 –Clock input (CLK) CLK input is a factor only for write operation During read, behaves as combinational logic block –Valid Address  Data Out valid after “access time” –Minor simplification of reality Clk Data In Write Enable 32 Data Out Address

23. CS224 Spring 2011 Some Logic Design… All storage elements have same clock –Edge-triggered clocking –“Instantaneous” state change (simplification!) –Timing always work if the clock is slow enough Cycle Time = Clk-to-Q + Longest Delay + Setup + Clock Skew Clk Don’t Care SetupHold............ SetupHold............

24. CS224 Spring 2011 Instruction Fetch (I.F.) RTL Common RTL operations –Fetch instruction Mem[PC]; Fetch instruction from memory –Update program counter Sequential PC <- PC + 4; Calculate next address

25. CS224 Spring 2011 Datapath: I.F. Unit 32 Instruction Word Address Instruction Memory PC Clk Adder 4

26. CS224 Spring 2011 Add RTL Add instruction add rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] <- R[rs] + R[rt]; Add operation PC <- PC + 4; Calculate next address OP=0rs rt rdsafunct Bits655556 first source register second source register result register shift amount function code (=32)

27. CS224 Spring 2011 Sub RTL Sub instruction sub rd, rs, rt Mem[PC]; Fetch instruction from memory R[rd] <- R[rs] - R[rt]; Sub operation PC <- PC + 4; Calculate next address OP=0rs rt rdsafunct Bits655556 first source register second source register result register shift amount function code (=34)

28. CS224 Spring 2011 Datapath: Reg/Reg Ops R[rd] <- R[rs] op R[rt]; –ALU control and RegWr based on decoded instruction –Ra, Rb, and Rd from rs, rt, rd fields 32 Result ALU control Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Instruction

29. OR Immediate RTL OR Immediate instruction ori rt, rs, imm Mem[PC]; Fetch instruction from memory R[rt] <- R[rs] OR ZeroExt(imm); OR operation with Zero-Extend PC <- PC + 4; Calculate next address OPrs rt imm Bits65516 first source register second register (dest) immediate

30. Datapath: Immediate Ops Rw set by MUX and ALU B set as busB or ZeroExt(imm) ALUsrc and RegDst set based on instruction Rd Rt 32 Result ALU control Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt (Don’t Care) RegDst ZeroExt Mux 32 16 imm16 ALUSrc ALU MUX

31. Load RTL Load instruction lw rt, rs, imm Mem[PC]; Fetch instruction from memory Addr <- R[rs]+SignExt(imm); Compute memory addr R[rt] <- Mem[Addr]; Load data into register PC <- PC + 4; Calculate next address OPrs rt imm Bits65516 first source register second register (dest) immediate

32. Datapath: Load Extender handles sign vs. zero extension of immediate MUX selects between ALU result and Memory output Rt Rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 5 55 RwRaRb 32 32-bit Registers RsRt (Don’t Care) RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32MemWr Mux MUX ALU

33. Store RTL Store instruction sw rt, rs, imm Mem[PC]; Fetch instruction from memory Addr <- R[rs]+ SignExt(imm); Compute memory addr Mem[Addr] <- R[rt]; Load data into register PC <- PC + 4; Calculate next address OPrs rt imm Bits65516 first source register second source register immediate

34. CS224 Spring 2011 Datapath: Store Register rt is passed on busB into memory Memory address calculated just as in lw case 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRt RegDst Extender 32 16 imm16 ALUSrc MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr Rt Rd Mux ALU MUX 32 MUX ExtOp

35. Branch RTL Branch instruction beq rs, rt, imm Mem[PC]; Fetch instruction from memory Cond <- R[rs] – R[rt]; Calculate branch condition if (Cond eq 0) Test if equal PC <- PC + 4 + SignExt(imm)*4; Calculate PC Relative address else PC <- PC + 4; Calculate next address OPrs rt imm Bits65516 first source second source immediate

36. CS224 Spring 2011 Datapath: Branch ExtOp ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt RegDst Extender 32 16 imm16 ALUSrc PC Clk Next Address Logic 16 imm16 Branch To Instruction Memory Zero More Detail to Come ALU MUX Rt Rd Mux

37. CS224 Spring 2011 The Next Address PC is byte-addressed in instruction memory –Sequential PC[31:0] = PC[31:0] + 4 –Branch operation PC[31:0] = PC[31:0] + 4 + SignExt(imm) × 4 Instruction Addresses –PC is byte addressed, but instructions are 4 bytes long –Therefore 2 LSBs of the 32 bit PC are always 0 –No reason to have hardware keep the 2 LSBs  Simplify hardware by using 30 bit PC Sequential PC[31:2] = PC[31:2] + 1 Branch operation PC[31:2] = PC[31:2] + 1 + SignExt(imm)

38. CS224 Spring 2011 Datapath: Fast, Expensive Next-I.F. Logic PC incremented to next instruction normally On beq instruction then can add immediate × 4 to PC + 4 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch Zero Addr[31:2] Instruction Memory Addr[1:0] “00” 32 Instruction[31:0] Instruction[15:0] 30 Adder MUX

39. Datapath: Slow, Smaller Next- I.F. Logic Slow because cannot start address add until ALU zero But probably not the critical path (LOAD is usually) 30 SignExt 30 16 imm16 “0” PC Clk 30 BranchZero Addr[31:2] Instruction Memory Addr[1:0] “00” 32 Instruction[31:0] 30 “1” Carry In Instruction[15:0] MUX Adder

40. CS224 Spring 2011 Jump RTL Jump instruction j target Mem[PC]; Fetch instruction from memory PC[31:2] <- PC[31:28] || target[25:0]; Calculate next address OPtarget Bits626 jump target address

41. Datapath: I.F. Unit with Jump MUX controls if PC is pseudodirect jump 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch Zero “00” Addr[31:2] Instruction Memory Addr[1:0] 32 26 4 PC[31:28] Target 30 Jump Instruction[15:0] Instruction[31:0] 30 Instruction[25:0] MUX Adder MUX Adder

42. CS224 Spring 2011 Putting it All Together 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr Instruction Fetch Unit Clk Zero Instruction[31:0] Jump Branch [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux

43. CS224 Spring 2011 A Real MIPS Datapath

44. CS224 Spring 2011 Control Design Next: Designing the Control for the Single Cycle Datapath Control Datapath Memory Processor Input Output

45. CS224 Spring 2011 Adding Control Analyze datapath and RTLs for control –Identify control points for pieces of the datapath Instruction Fetch Unit Integer function units Memory –Categorize type of control signal Flow of data through multiplexors Writes of state information –Derive control signal values for each instruction Design and implement control with logic/PLA/ROM (for single cycle & pipelined)

46. Instruction Fetch (first part) Always fetch next instruction Mem[PC]; 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch = previous Zero = previous “00” Addr[31:2] Instruction Memory Addr[1:0] 32 26 4 PC[31:28] Target 30 Jump = previous Instruction[15:0] Instruction[31:0] 30 Instruction[25:0] MUX Adder MUX 1 0 0 1 Adder

47. 5 Control for Arithmetic 32 ALUctr = Clk busW RegWr = 1 32 busA 32 busB 55 RwRaRb 32 32-bit Registers Rs Rt RegDst = 1 Extender 32 16 imm16 ALUSrc = 0 ExtOp = X MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 0 Branch = 0 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

48. Instruction Fetch at End Increment PC : PC = PC+4; (for all but Branch/Jump) 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch = 0 Zero = X “00” Addr[31:2] Instruction Memory Addr[1:0] 32 26 4 PC[31:28] Target 30 Jump = 0 Instruction[15:0] Instruction[31:0] 30 Instruction[25:0] MUX Adder MUX 0 1 1 0 Adder

49. Control for Immediate ( ori ) 32 ALUctr = Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt RegDst = 0 Extender 32 16 imm16 ALUSrc=1 ExtOp=0 MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 0 Branch = 0 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

50. 5 Control for Load ( lw ) 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 55 RwRaRb 32 32-bit Registers Rs Rt RegDst = 0 Extender 32 16 imm16 ALUSrc = 1 ExtOp = 1 MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 0 Branch = 0 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

51. 5 Control for Store ( sw ) 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 55 RwRaRb 32 32-bit Registers Rs Rt RegDst = X Extender 32 16 imm16 ALUSrc = 1 ExtOp = 1 MemtoReg = X Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 0 Branch = 0 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

52. 55 Control for Branch ( beq ) 32 ALUctr = Sub Clk busW RegWr = 0 32 busA 32 busB 5 RwRaRb 32 32-bit Registers Rs Rt RegDst = X Extender 32 16 imm16 ALUSrc = 0 ExtOp = X MemtoReg = X Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 0 Branch = 1 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

53. Instruction Fetch ( beq ) Consider the interesting case where we branch (Zero = 1) 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch = 1 Zero = 1 “00” Addr[31:2] Instruction Memory Addr[1:0] 32 26 4 PC[31:28] Target 30 Jump = 0 Instruction[15:0] Instruction[31:0] 30 Instruction[25:0] MUX Adder MUX 0 1 1 0 Adder

54. 555 Control for Jump ( j ) 32 ALUctr = X Clk busW RegWr = 0 32 busA 32 busB RwRaRb 32 32-bit Registers Rs Rt RegDst = X Extender 32 16 imm16 ALUSrc = X ExtOp = X MemtoReg = X Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 Instruction Fetch Unit Clk Zero Instruction[31:0] Jump = 1 Branch = 0 [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

55. Instruction Fetch ( j ) 30 SignExt 30 16 imm16 “1” PC Clk 30 Branch = 0 Zero = X “00” Addr[31:2] Instruction Memory Addr[1:0] 32 26 4 PC[31:28] Target 30 Jump = 1 Instruction[15:0] Instruction[31:0] 30 Instruction[25:0] MUX Adder MUX 0 1 1 0 Adder

56. CS224 Spring 2011 555 Control Path 32 ALUctr Clk busW RegWr 32 busA 32 busB RwRaRb 32 32-bit Registers Rs Rt RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr Instruction Fetch Unit Clk Zero Instruction[31:0] Jump Branch [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1

57. CS224 Spring 2011 Summary of Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Sub 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Sub x x x 0 0 0 1 x xxx func op 00 0000 00 110110 001110 101100 010000 0010 coding from green card 10 000010 0010 Not Important

58. CS224 Spring 2011 Multilevel Decoding 12-input control will be very large (2 12 = 4096) To keep decoder size smaller, decode some control lines in each stage Since only R-type instructions (with op = 000000) need function field bits, give these to ALU control func Main Control op 6 ALU Control (Local) N 6 ALUop ALUctr 3 ALU

59. CS224 Spring 2011 Multilevel Decoding: Main Control Table

60. The Encoding of ALUop In this exercise, ALUop has to be 2 bits wide to represent: –(1) “R-type” instructions –“I-type” instructions that require the ALU to perform: (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop has to be 3 bits wide to represent: –(1) “R-type” instructions –“I-type” instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (e.g. andi) Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx

61. CS224 Spring 2011 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than ALUctr ALU

62. Truth Tables R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than

63. CS224 Spring 2011 The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func This makes func a don’t care

64. CS224 Spring 2011 The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 ALUctr = !ALUop & !ALUop + ALUop & !func & !func

65. CS224 Spring 2011 The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

66. CS224 Spring 2011 The ALU Control Logic ALU Control (Local) func 3 6 ALUop ALUctr 3 ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUctr = !ALUop & !ALUop + ALUop & !func & !func ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

67. Main Control Truth Table Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc :

68. CS224 Spring 2011 Truth Table for RegWrite R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

69. CS224 Spring 2011 PLA Implementation RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

70. CS224 Spring 2011 Implementing Control Programmable Logic Array (PLA) vs. “Random Logic” –Design Changes Validation changes are common PLA is less work to change; area/timing impact is predictable –Area Tradeoff depends on complexity of logic (# of gates) –Timing and Power Random logic generally better since individual paths can be tuned Alternative approach is Read Only Memory (ROM/PROM) –Also combinational, but size makes it slow –used for microcoded control with more than one state/cycle per instruction

71. CS224 Spring 2011 555 Putting It All Together 32 ALUctr Clk busW RegWr 32 busA 32 busB RwRaRb 32 32-bit Registers Rs Rt RegDst Extender 32 16 imm16 ALUSrc ExtOp MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr Instruction Fetch Unit Clk Zero Instruction[31:0] Jump Branch [21:25][16:20][11:15] [0:15] Imm16RdRsRt MUX ALU Rt Rd Mux 1 0 0 1 0 1 Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr[5:0] Instr[31:26]

72. Worst Case Timing (Load) Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value Data Mem AddressOld ValueNew Value busWOld Value New Sum of {Mux Delay+setup+skew} Delay through Extender & Mux RegisterWrite Occurs --- > Data Memory Access Time

73. CS224 Spring 2011 Single Cycle Processor Advantages –Single cycle per instruction makes logic and clock simple –All machines would have a CPI of 1 Disadvantages –Inefficient utilization of memory and functional units since different instructions take different lengths of time Each functional unit is used only once per clock cycle e.g. ALU only computes values a small amount of the time –Cycle time is the worst case path  long cycle times! Load instruction –PC CLK-to-Q + –instruction memory access time + –register file access time + –ALU delay + –data memory access time + –register file setup time + –clock skew –All machines would have a CPI of 1, with cycle time set by the longest instruction!

74.  Single cycle datapath => CPI=1, CCT => long  5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic  Control is the hard part  MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output