ECE 551 Fall /6/2001 ECE Digital System Design & Synthesis Lecture 2 - Pragmatic Design Issues Overview  Classification of Issues oThree-State and Other Hi-Z States oSequential Circuit Basics oAsynchronous Circuits oClock Design oElectrical Issues  Miscellaneous problems that arise in design and their solutions

ECE 551 Fall /6/2001 Three-State and Other Hi-Z States  Three-state conflicts  Floating three-state nets and inputs  Pull-ups and Pull-downs  Bus keepers

ECE 551 Fall /6/2001 Three-State Conflicts  What are they and what are their effects? oStatic – Chip damage or static power consumption oDynamic – Dynamic or static power consumption D0 D1 E0 E1 OUT E0 E1 E0 E

ECE 551 Fall /6/2001 Three-State Conflicts (continued)  How can conflicts be avoided? oStatic – Decoded enable signals oDynamic – Delay control D0 D1 E0 E1 OUT E0 E1 E0 E

ECE 551 Fall /6/2001 Floating Inputs and Three- State Nets  Floating input values on gates can cause: ostatic power dissipation ohigh-frequency switching that induces power supply noise  Floating input values arise from: oGate inputs, e. g., for example on exterior of IC, that are not connected oLines driven by 3-state buffer or gate outputs, all of which are in the Hi-Z state.

ECE 551 Fall /6/2001 Floating Inputs and Three- State Nets (continued)  How can floating inputs and nets be avoided? oUse a pull-up or pull-down resistor or transistor with a fixed gate voltage value.  Advantage – simple  Disadvantages – static power dissipation and loading of node oOn internal lines, particularly buses, use a bus keeper (weak buffer)

ECE 551 Fall /6/2001 Sequential Circuit Basics  Non-D flip-flops  Multi-phase clocks  Mixed-edge clocking  Multiple clocks  System initialization process

ECE 551 Fall /6/2001 Non-D flip-flops  D Flip-Flops oUnique characteristic – the typical master-slave DFF is also functionally an edge-triggered DFF.  Non- D Flip-Flops (JK, T, etc.) oIn the cell libraries, these flip-flop may be full-custom designs or may simply consist of a DFF with added logic. oIf it is just a DFF with added logic, you might as well design for a DFF to give the logic optimization software more flexibility.

ECE 551 Fall /6/2001 System Initialization Process  Flip-flop initialization oOccurs at power-up or at reset oWhich of the following flip-flops need to be initialized immediately on power-up or reset:  Sequencing circuit in the control unit?  Register file in the datapath?  Program counter? oHow are the other flip-flops initialized? No Yes

ECE 551 Fall /6/2001 System Initialization Process (continued)  Flip-flop initialization oHow are flip-flops initialized?  By using direct set and direct reset inputs on the flip-flops (typically need only one or the other)  Suppose that a FF is to be initialized to 1 and there are only library cells with with direct reset. What can you do? D CLK Q D C Q R RESET

ECE 551 Fall /6/2001 Mixed-Edge Clocking  Clocking on both: oPositive and negative edges, or oPositive and negative pulses  In some cases may be useful to: oObtain two event triggers per clock cycle oDeal with certain nasty timing problems such as hold time difficulties  Confusing and more difficult to handle when using tools  Quantizes time and adds FF delay time much as pipelining does, so can reduce speed unless throughput is the issue as with pipelining

ECE 551 Fall /6/2001 Multi-Phase Clocks  Uses oAs primary clocking approach using latches oAs means to solve special timing problems CLCL C LC L Latches     CL - Combinational Logic

ECE 551 Fall /6/2001 Multiple Clocks  Typical in sophisticated circuit  Example - Microprocessor o133 MHz External o1 GHz Internal  Potential for synchronization problems between clocking domains