1. ECE 551 Fall 2001 19/6/2001 ECE 551 - Digital System Design & Synthesis Lecture 2 - Pragmatic Design Issues Part 2 Overview  Issues considered in this part oAsynchronous Circuits oClock Design and Delays oElectrical Issues  Miscellaneous problems that arise in design and their solutions

2. ECE 551 Fall 2001 29/6/2001 Asynchronous Circuits  Delay-dependent design  Combinational hazards  Level/pulse conversion  Synchronization  Memory timing

3. ECE 551 Fall 2001 39/6/2001 Delay-Dependent Design A DA A A A

4. ECE 551 Fall 2001 49/6/2001 Combinational Hazards  Hazard in a Multiplexer A C F B 1 1 B F

5. ECE 551 Fall 2001 59/6/2001 Combinational Hazards (continued)  Classification of Combinational Hazards oStatic oDynamic oEssential  Consequences of Hazards oSignals with hazards in or entering asynchronous environments  Hazard Prevention oRedundant Logic oDelay Control

6. ECE 551 Fall 2001 69/6/2001 Level/Pulse Conversion DATA_IN DATA_OUT D QC Clock  Level on DATA_IN must be longer than a clock period and must not rise close to the positive clock edge. Ideally synchronous with the Clock.

7. ECE 551 Fall 2001 79/6/2001 Synchronization D Q C Clock D Q C Req Rep Clock  Asynchronous Rep can cause sequential circuit malfunction since it reaches two or more flip-flops.  Solution: Put synchronizer (PET DFF) in Rep path.

8. ECE 551 Fall 2001 89/6/2001 Metastability  A specific phenomena that in the present of certain closely timed events on the inputs can cause bizarre latch and flip-flop behavior: oHanging for a time at a threshold level oProduce a damped oscillation  One remedy: Use two to three synchronizers in series

9. ECE 551 Fall 2001 99/6/2001 Memory Timing  Many memories are asynchronous circuits, e. g., SRAMs are latch-based without a clock on the latch o Their inputs can respond to “glitches” such as hazards. o A majority of all memory inputs need to be “glitch-free.”  Since memories involve capture of data in selectively- addressed cells, set-up and hold times apply to many of the inputs, notably the addresses.  Memory outputs often involve 3-state buses; one must be sure that the bus is active whenever data is being read.  When designing with memories, careful attention must be given to meeting fully all of the timing specifications.

10. ECE 551 Fall 2001 109/6/2001 Asynchronous Design  Using classical techniques, because of the difficulty of eliminating the hazards, very difficult to insure correct operation under all timing possibilities  Therefore, don’t do it!  If you truly need it, investigate some of the more contemporary approaches which avoid some of the many difficulty.

11. ECE 551 Fall 2001 119/6/2001 Clocking Design  Clock skew  Clock gating  Clock jitter  Clock buffers  Interconnect delay control

12. ECE 551 Fall 2001 129/6/2001 Clock Skew  Clock skew is the arrival of the active clock edge(s) at different times in different parts of a chip or system.  Clock skew can result from ologic delays, as in clock gating and buffering ointerconnection delays.  Clock skew can cause: oPremature capture of new “state” values oThe shortening of the effective allowable delay along a path from flip-flop to flip-flop oLengthening of the effective allowable delay along a path from flip-flop to flip-flop

13. ECE 551 Fall 2001 139/6/2001 Clock Gating  Use of gate logic to interrupt the clock signal to a portion of the logic to prevent the state from changing  Why use it? oSimplifies logic oReduces power consumption  Why not use it? oCan circuit failure due to clock skew oComplicates circuit testing

14. ECE 551 Fall 2001 149/6/2001 Clock Jitter  Clock does not provide a signal having a fixed frequency. Clock period is: oslightly shorter, or oslightly longer on any given cycle.  The clock jitter is the absolute value of the maximum difference between othe nominal period, and othe shortest and the longest clock periods  Can be very serious if circuit has multiple clocks with independent jitter.

15. ECE 551 Fall 2001 159/6/2001 Combinational Logic Delay Upper Bound  Components of the Bounds oNominal Clock Period CP oFF Propagation Delay t FF oFF Set-up Time t SU oClock skew (of destination FF clock with respect to source FF clock) (+ or –) t sc oClock Jitter Magnitude t CJ  Combinational Logic Delay Upper Bound along Particular FF to FF path: oD CL < CP + t sc – t CJ – t FF – t SU  From this equation, we see that: oClock jitter degrades performance oClock skew may either degrade (if negative) or enhance (if positive) performance!

16. ECE 551 Fall 2001 169/6/2001 Combinational Logic Delay Lower Bound  Related to incorrect function due to hold time violation  Left as an exercise

17. ECE 551 Fall 2001 179/6/2001 Clock Buffers  Reasons for buffering oLarge driven load oLong clock interconnects  Must be designed to minimize skew  Overall, clock distribution in an aggressive design is a major separate task

18. ECE 551 Fall 2001 189/6/2001 Interconnect Delay Control  Interconnect delay (exclusive of clocks) for “global” interconnects is a significant component of the FF to FF delay in submicron channel length circuits.  Implication: Interconnect delay has a significant impact on performance in submicron channel length designs. oIdeally global routes are from FF to FF. oIf combinational logic involved, all interconnect delay subtracted from combinational logic delay upper bound

19. ECE 551 Fall 2001 199/6/2001 Interconnect Delay Control (continued)  Methods of handling interconnect delay: oChip floorplanning to reduce global routing oInterconnect driver strength and inserted buffers oInterconnect sizing oCircuit retiming (if combinational logic in series with global interconnect) oLast resort: addition of FFs to very troublesome paths and redesign of parts of system affected.

20. ECE 551 Fall 2001 209/6/2001 Electrical Issues  Loading  Constant inputs  Slew rate and ground bounce

21. ECE 551 Fall 2001 219/6/2001 Loading  The loading of a gate or other component can affect: oOutput levels oLocal Power Dissipation oDelay  Consider two logic families assuming both loads and drivers are in the families: oTTL oCMOS

22. ECE 551 Fall 2001 229/6/2001 Loading of TTL Gates  TTL (Transistor-Transistor Logic) is a current sinking technology.  For driven TTL gates, at LOW, a substantial current flows out of inputs into the driving output.  The static current for the driving gate at LOW: oI C = V CC /(R C + R B /FO) where R C is the output resistance of the TTL driver transistor in saturation, R B is the resistance in the driven gates governing the input current, and FO is the fanout in terms of number of gates driven.

23. ECE 551 Fall 2001 239/6/2001 Loading of TTL Gates  As FO increases, the current increases which increases: othe LOW output level othe power dissipation  Also, the additional gates driven add to the capacitance driven which increases delay.  The increase in the low level can cause noise problems.  The increase in power dissipation can cause thermal problems and possible IC damage.

24. ECE 551 Fall 2001 249/6/2001 Loading of CMOS Gates  The current into or out of a CMOS gate output flows only during transitions and is otherwise negligible.  Increased fanout FO increases the capacitive load on the driving gate which increases: othe delay of a transition othe duration of time during which a sizable current flows into or out of the driving gate.  If the output changes frequently, then the dynamic current could cause power dissipation to produce a local thermal problem and possible IC damage.

25. ECE 551 Fall 2001 259/6/2001 Constant Inputs  If a constant input is to be applied to an IC from outside, it is generally a good idea to include a resistance between the ground or supply and the input for the following reasons: oprevents a large current at the input for some technologies at power-up that can cause damage or disable the IC. oallows the fixed signal to be changed during testing.

26. ECE 551 Fall 2001 269/6/2001 Slew Rate and Ground Bounce  If large dynamic currents are drawn from the power supply, there can be significant changes in the GND or VCC voltage values on chip due to lead inductance.  This phenomena is called ground bounce in the case of the ground voltage.  The high current problem most often arises with output buffers driving large off-chip capacitances.

27. ECE 551 Fall 2001 279/6/2001 Slew Rate and Ground Bounce Remedies  The voltage transient is related to: oL dI/dt where I is the power or ground current.  Reduce the effective lead inductance L by using multiple supply and ground leads. oIt is not uncommon for a significant percentage of all leads on an IC to be supply or ground leads.  Reduce dI/dt by reducing the slew rate, the rate of change in the output voltage. oBy reducing C dV/dt, the current and its derivative are reduced.

28. ECE 551 Fall 2001 289/6/2001 Summary  Design Issues oThree-State and Other Hi-Z States oSequential Circuit Basics oAsynchronous Circuits oClock Design oElectrical Issues  All are important  Far from exhaustive

29. ECE 551 Fall 2001 299/6/2001 References  Seidensticker, Robert B., The Well-Tempered Digital Design, Addison-Wesley Publishing Company, 1986.  Wakerly, John F., Digital Design - Principles and Practices, 3rd Ed., Prentice-Hall, 2000.  Johnson, Howard W., and Martin Graham, High- Speed Digital Design – A Handbook of Black Magic, Prentice Hall PTR, 1993.