1. Synchronous Sequential Circuits by Dr. Amin Danial Asham

2. References  Digital Design 5 th Edition, Morris Mano

3.  Sequential Circuits  A Sequential circuit consists of a combinational circuit and memory elements that are connected to the combinational circuit forming a feed back path.  Memory elements store binary information.  The stored binary information called at any time instant is the state of the sequential circuit.  Hence the output of a sequential circuit and the next state are functions of the external inputs and the present state stored in the memory elements.

4.  Sequential Circuits ( continue )  There are two types of sequential circuits:  A synchronous sequential circuit, which has a behavior that can be defined by knowing its input and state at discrete time instants determined by a clock pulses.  An asynchronous Sequential circuit, which has a behavior determined by knowing its input and state at any instant and the order of input change.

5.  Asynchronous Sequential Circuits  Memory (storage) elements in synchronous sequential circuits are clocked flip-flop’s.  A flip-flop stores a binary value. Therefore, a single flip-flip stores either 1 or 0.  A sequential circuit may use any number of flip-flops’s to store the required number of bits.  The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).

6.  Memory Elements  Memory elements store binary information in the form of either 1 or 0 for an indefinite time period as long as there is power to the storing circuit.  Each memory element stores a binary bit.  Memory elements are classified into two types based on how are they controlled: o Latches: are controlled by the input signal levels. Latches are level sensitive to input signals. Therefore, these elements are asynchronous elements. o Flip-flop: are triggered by the clock transitions and hence these elements are synchronous. Therefore, flip- flops are edge sensitive to clock signal.

7.  NOT Gate SR Latch  There are two input signal S (set) and R(reset): o S=1 and R=0 set the output Q to 1 and the output complement Q’ to 0 (Set State) o S=0 and R=1 set the Q to 0 and the complement Q’ to 1 (Reset State) o When both S and R are 0’s the current value is stored. o When both S and R are 1’s both Q and Q’ are 0’s which is forbidden.

8.  NOT Gate SR Latch(continue)  Why both S and R are forbidden to be set to 1 for NOR SR Latch? o In case of both S and R are 1’s at the same time, both Q and Q’ are zeros at the same time. o If then both S and R returned back to 0’s simultaneously the device enters unpredictable state.  SR latch has two useful states Set state and Reset state. 1 1 0 0 0 0 ? ? 0 0

9.  NOT Gate SR Latch

10.  NAND Gate SR Latch (continue)  SR Latch can be also implemented by NAND gates.  There are two input signal S (set) and R(reset): o S=1 and R=0 set the output Q to 0 and the output complement Q’ to 1 (Reset State). o S=0 and R=1 set the Q to 1 and the complement Q’ to 0 (Set State). o When both S and R are 1’s the current value is stored. o When both S and R are 0’s both Q and Q’ are 1’s which is forbidden.

11.  NAND Gate SR Latch (continue)  Why both S and R are forbidden to be set to 0 for NAND SR Latch? o In case of both S and R are 0’s, both Q and Q’ become 1’s. o If then both S and R returned back to 1’s simultaneously the device enters unpredictable state.  SR latch has two useful states Set state and Reset state. 0 0 1 1 1 1 ? ? 1 1

12.  NAND Gate SR Latch (continue)

13. Basic NAND Latch 0 1 1 1  SR Latch With Enable:  En signal is added to enable and disable the latch, that is, in case of En= 0 the latch is disabled and hence the output does not change with the input signals.  When En= 0 the 1’ are fed to the set and reset of the original NAND latch circuit and hence the output is stored and not affected by the inputs  When En=1 both S and R signals are fed to the original NAND latch in inverted form.

14.  SR Latch With Enable (continue)  In case of S, R, En are 1’s, the basic latch is fed by 0’s on both set and rest signals and hence both outputs are on 1’s (forbidden).  If then En is back to 0 then the inputs to the basic latch becomes ones which puts the latch into unpredictable state and the next state depends on which one of S and R becomes zero first. Basic NAND Latch 1 1 1 0 0 1 1 1 1 0 1 1 ? ?

16.  D-Latch (continue)

17.  The changes of the output of the latch follows the changes of the input D during the enable input En is at level high.  Therefore, latches are level sensitive devices.

18. Negative Edge Triggered D-FF 1 D 0 D 0 1

19.  Edge Triggered D Flip-Flops: Master Slave (continue)

20.  The behavior of the Master Slave D FF can be described as follows: o The output of the flip flop is changed once since a fixed value Y is transferred to the output, which is stored immediately before the falling edge of the clock. Therefore input changes after falling edge has no effect since master latch is disabled and Y is locked. o A change in the output is triggered by the negative edge of the clock. o The output change may complete only during the negative level of the clock.  A positive edge Master-Slave D-FF is: Positive Edge Triggered D-FF

21.  Edge Triggered D Flip-Flops: Master Slave (continue)

22.  Positive Edge Triggered D Flip-Flop (continue)  This is another design of positive edge trigger D-FF, which consists of three SR latches.  Upper and Lower latches are connected to the Clk and D signal. 0 1 1 1 D’ D D D  In case of Clk=0, 1’s are applied to the inputs of the output SR latch and hence Q and Q’ are locked to the previous values.  In case of Clk=1, the input signal is D is stored in the first stage SR latches (Upper and Lower latches) and transferred to the output latch. Output Latch Upper Latch Lower Latch

23.  Edge Triggered D Flip-Flop Symbols

24.  Important Flip-Flop Parameters  Setup time (t su ) is the minimum amount of time the data signal should be held steady before the clock transition.  Hold time (t h ) is the minimum amount of time the data signal should be held steady after the clock transition. thth t su tptp  Propagation delay (t p ) is the time a flip-flop takes to change its output after the clock trigger edge to the stabilized new state. Clk Q D

26.  Other types of Flip-Flops (continue)  Toggle Flip Flop Characteristic Table

27.  Other types of Flip-Flops (continue)  Flip-Flop with Direct Inputs 0 1 1  Direct inputs drive the FF to a certain state independently of the clock.  Direct Set or Preset drive the FF to set state (Q=1 and Q’=0)  Direct Reset or Clear drive the FF to reset state (Q=0 and Q’=1)  Direct inputs are useful to set the FF to a certain state after turning the power on because the state is unknown at that case.

30. Thanks