# 11/16/2004EE 42 fall 2004 lecture 331 Lecture #33: Some example circuits Last lecture: –Edge triggers –Registers This lecture: –Example circuits –shift.

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11/16/2004EE 42 fall 2004 lecture 331 Lecture #33: Some example circuits Last lecture: –Edge triggers –Registers This lecture: –Example circuits –shift registers –Counters –adders

11/16/2004EE 42 fall 2004 lecture 332 Examples of useful combinatorial circuits There are several patterns of combinatorial logic which appear fairly often, here are several examples The examples will be given in terms of gates as well as logic equations, but not in a minimal representation, but just a clear example In most cases, a computer program such as Verilog would be responsible for producing optimal implementations anyway.

11/16/2004EE 42 fall 2004 lecture 333 Pattern recognizer The output of this pattern recognition circuit is 1 only if the input is 10110, and otherwise zero ABCDEABCDE Q

11/16/2004EE 42 fall 2004 lecture 334 Decoder n inputs, 2 n outputs –one output is 1 for each possible input pattern, all other outputs are 0 ABO1O1 O2O2 O3O3 O4O4 001000 010100 100010 110001

11/16/2004EE 42 fall 2004 lecture 335 Decoder n inputs, 2 n outputs –one output is 1 for each possible input pattern, all other outputs are 0 ABAB 12341234

11/16/2004EE 42 fall 2004 lecture 336 CMOS switch A CMOS switch will allow a logic level to pass if activated, does not allow current through the gate if not activated

11/16/2004EE 42 fall 2004 lecture 337 Multiplexer (MUX) n-bit selector and 2 n inputs, one output –output equals one of the inputs, depending on selector I1I2I3I4I1I2I3I4 2 input decoder ABAB O

11/16/2004EE 42 fall 2004 lecture 338 Buffer A buffer passes a logic level while increasing its drive capability A design like the previous slide would likely be implemented with a buffer at its output Often, wider transistors in the second stage

11/16/2004EE 42 fall 2004 lecture 339 Half Adder A half adder takes two bits and produces their sum, with a carry It is called a half adder because it does not have a carry input ABAB Sum Output Carry out

11/16/2004EE 42 fall 2004 lecture 3310 Half adder ABOC 0000 0110 1010 1101

11/16/2004EE 42 fall 2004 lecture 3311 Full Adder Add two bits and carry-in, produce one-bit sum and carry-out. ABC in SC out 00000 00110 01010 01101 10010 10101 11001 11111

11/16/2004EE 42 fall 2004 lecture 3312 One bit Full adder A single bit full adder can be made from two half adders and an or gate Half adder A B O C Sum out C Carry out Carry in

11/16/2004EE 42 fall 2004 lecture 3313 Full adder as a logic block We can use our full adder as a logic block to make a multi-bit adder by cascading the carry line Full adder (one bit) C in A B C out Sum

11/16/2004EE 42 fall 2004 lecture 3314 Three-bit Adder half adder (one bit) A0A0 B0B0 Sum 0 Carry Full adder (one bit) A1A1 B1B1 Sum 1 Carry Full adder (one bit) A2A2 B2B2 Sum 2 Carry

11/16/2004EE 42 fall 2004 lecture 3315 Adders It is interesting to note that in hardware, it is typical to dedicate an adder for one particular use, as contrasted with software on a CPU, where numbers are moved around to be added by a central adder. This is because the additional selectors and wires to move around numbers takes more area than just putting in separate adders for each purpose.

11/16/2004EE 42 fall 2004 lecture 3316 Some register based digital blocks There are also several common digital blocks which are based around flip-flop registers, such as multi-bit data registers, shift registers, and counters

11/16/2004EE 42 fall 2004 lecture 3317 Definition:Register A register is a collection of flip-flops with similar controls and logic A register stores a multi-bit value. –Stored values somehow related (e.g., form binary value) –Share clock, reset, and set lines –Similar logic at each stage

11/16/2004EE 42 fall 2004 lecture 3318 RSRSRS DQDQDQDQ OUT1OUT2OUT3OUT4 Write enable IN1IN2IN3IN4 RS Reset “0” Registers Example: a collection of D-flip-flops, all controlled by a common write enable (WE). –When WE transitions from 1 to zero (falling edge), a n-bit value D is written to register.

11/16/2004EE 42 fall 2004 lecture 3319 DQDQDQDQ IN OUT shift Shift Register Holds samples of past input values and shifts them in sequence into a string of flip- flops

11/16/2004EE 42 fall 2004 lecture 3320 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK Shift Register Holds samples of input –Store input values in sequence –4-bit shift register used as a serial to parallel converter:

11/16/2004EE 42 fall 2004 lecture 3321 RSRSRS DQDQDQDQ Shift IN1 RS Reset “0” Parallel to serial converter MUX “0” literal IN2 MUX IN3IN4 Load/Shift Output

11/16/2004EE 42 fall 2004 lecture 3322 parallel inputs parallel outputs serial transmission Shift Register Application Parallel-to-serial conversion for serial transmission

11/16/2004EE 42 fall 2004 lecture 3323 DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK OUT Pattern Recognizer Combinational function of input samples –In this case, recognizing the pattern 1001 on the single input signal

11/16/2004EE 42 fall 2004 lecture 3324 Use of counters Counters are often used when something needs to happen a certain number of times. Counters can be designed to be preset to particular values, to count up or down, and/or to trigger some action at a particular count by the use of a pattern recognizer.

11/16/2004EE 42 fall 2004 lecture 3325 Binary Counter Logic between registers (not just multiplexer) –XOR decides when bit should be toggled –Always for low-order bit, only when first bit is true for second bit, and so on

11/16/2004EE 42 fall 2004 lecture 3326 Sequential Logic Summary Fundamental building block of circuits with state –R-S latch, R-S master/slave, D master/slave, edge-triggered D FF –Latch and flip-flop Timing methodologies –Use of clocks –Cascaded FFs work because prop delays exceed hold times –Beware of clock skew Asynchronous inputs and their dangers –Synchronizer failure: what it is and how to minimize its impact Basic registers –Shift registers –Pattern detectors –Counters

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