1. 1 ECE 551: Digital System Design & Synthesis Spring 2003 Lecture Materials Prepared by: Charles Kime, Kewal Saluja and Michael Schulte

2. 1/16/2003 ECE 551 Spring 2003 2 ECE 551: Digital System Design & Synthesis  Lecture Set 1: oIntroduction oOverview of Contemporary Digital Design oPragmatics 1

3. 1/16/2003 ECE 551 Spring 2003 3 ECE 551 - Digital System Design & Synthesis Lecture 1.1 - Introduction  Overview oCourse Purpose oCourse Topics oCourse Tools oCourse Info

4. 1/16/2003 ECE 551 Spring 2003 4 Course Purpose  To provide knowledge and experience in performing contemporary logic design based on oHardware description languages (HDLs) oHDL simulation oAutomated logic synthesis oTiming analysis  With consideration for oPractical design and test issues oChip layout issues oDesign reuse for system-on-a-chip (SoC)

5. 1/16/2003 ECE 551 Spring 2003 5 Course Topics  Pragmatics of Digital Design  Hardware Modeling with the Verilog HDL  Event-Driven Simulation and Testbenches  Verilog Language Constructs and Delay  Behavioral Descriptions in Verilog  An Overview of VHDL  Logic Synthesis and Timing  Physical Design and Design Reuse

6. 1/16/2003 ECE 551 Spring 2003 6 Course Tools  Modelsim HDL Simulation Tools (Mentor)  Design Analyzer Synthesis Tools (Synopsys)  G11 Technology Library (LSI Logic)

7. 1/16/2003 ECE 551 Spring 2003 7 Course Information  Course Conduct Course Conduct  Standard Reference Standard Reference  The above plus all other course material can be found at http://courses.engr.wisc.edu/ecow/g et/ece/551/kime/ http://courses.engr.wisc.edu/ecow/g et/ece/551/kime/  Be familiar with all!

8. 1/16/2003 ECE 551 Spring 2003 8 Lecture 1.2 – Contemporary Digital Design  Overview oLayout Lite oApplication Specific Integrated Circuit (ASIC) Technologies oIC Costs oASIC Design Flows  The Role of HDLs and Synthesis  The Role of IP Cores and Reuse  The Role of Physical Design oSummary

9. 1/16/2003 ECE 551 Spring 2003 9 Layout Lite - 1  IC are produced from masks that correspond to geometric layouts produced by the designer or by EDA tools.  In CMOS, a typical IC cross-section: Substrate Oxide Transistor Metal 3 Metal 2 Metal 1 Polysilicon Diffusion Channel

10. 1/16/2003 ECE 551 Spring 2003 10 Layout Lite - 2  The layout corresponding to the cross-section: oThe transistor is outlined in broad yellow lines. oEverything else is interconnect. Channel Transistor

11. 1/16/2003 ECE 551 Spring 2003 11 IC Implementation Technologies STANDARD IC FULL CUSTOM SEMI - CUSTOM FIELD PROGRAMMABLE STANDARD CELL GATE ARRAY, SEA OF GATES ASICFPGAPLD

12. 1/16/2003 ECE 551 Spring 2003 12 Distinguishing Features of IC Technologies - 1  Implementation technologies are distinguished by: oThe levels of the layout 1) transistors and 2) interconnect that are:  Common to distinct IC designs (L1)  Different for distinct IC designs (L2) oThe use of predesigned layout cells  Predesigned cells are used (P1)  Predesigned cells are not used (P2)

13. 1/16/2003 ECE 551 Spring 2003 13 Distinguishing Features of IC Technologies - 2  Implementation technologies are distinguished by: oMechanism used for instantiating distinct IC designs:  Metallization (M)  Fuses or Antifuses (F)  Stored Charge (C)  Static Storage (R)

14. 1/16/2003 ECE 551 Spring 2003 14 Technologies in Terms of Distinguishing Features - 1  Full Custom – P2, M oTransistors – L2, Interconnects – L2  Standard Cell – P1, M oTransistors – L2, Interconnects – L2  Gate Array, Sea of Gates – P1, M oTransistors – L1, Interconnects – L2

15. 1/16/2003 ECE 551 Spring 2003 15 Technologies in Terms of Distinguishing Features - 2  FPGA – P1, F or R oTransistors – L1, Interconnects – L1  PLD – P1, F or C oTransistors – L1, Interconnects – L1

16. 1/16/2003 ECE 551 Spring 2003 16 Technologies in Terms of Shared Fabrication Steps  Custom Fabricated Layers oFull Custom and Standard Cells – all layers are custom fabricated oGate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated oFPGAs and PLDs – nothing is custom fabricated  Consequences due to economy-of-scale: oFab costs reduced for Gate Arrays and Sea of Gates oFab costs further reduced for FPGAs and PLDs

17. 1/16/2003 ECE 551 Spring 2003 17 Layout Styles - 1  Technologies in terms of layout styles: Adjustable Spacing Megacells Standard Cell Gate Array - Channeled … … Fixed Spacing Base Cell

18. 1/16/2003 ECE 551 Spring 2003 18 Layout Styles - 2  Technologies in terms of layout styles: … Base Cell Gate Array - Channel-less (Sea of Gates) Gate Array - Structured … … Fixed Embedded Block

19. 1/16/2003 ECE 551 Spring 2003 19 IC Costs - 1  An example: 10,000 gate circuit [1] oFixed costs  Standard Cell - $146,000  Gate Array - $86,000  FPGA - $21,800 oVariable costs  Standard Cell - $8 per IC  Gate Array - $10 per IC  FPGA - $39 per IC

20. 1/16/2003 ECE 551 Spring 2003 20 IC Costs - 2  An example: 10,000 gate circuit

21. 1/16/2003 ECE 551 Spring 2003 21 IC Costs – 3  Why isn’t FPGA cheaper per unit due to economy-of-scale? oThe chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design. oThe larger the chip area, the poorer the yield of working chips during fabrication oAlso, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies.

22. 1/16/2003 ECE 551 Spring 2003 22 Draw Datapath Schematics * ASIC Design Flow - Traditional Write Specifications Define System Architecture Partition - Data- path &Control Define State Diag/Tables Draw Control Schematics * Integrate Design* Do Physical Design* Implement* * Steps followed by validation and refinement

23. 1/16/2003 ECE 551 Spring 2003 23 Traditional Flow Problems  Schematic Diagrams oLimited descriptive power  State Diagrams and Algorithmic State Machines oLimited portability oLimited complexity oDifficult to describe parallelism oLimited complexity  Time-Intensive and Hard to Update

24. 1/16/2003 ECE 551 Spring 2003 24 How about HDLs Instead of Diagrams? - 1  Hardware description languages (HDLs) oComputer-based programming languages oModel and simulate the functional behavior and timing of digital hardware oSynthesizable into a technology-specific netlist  Two main HDLs used by industry oVerilog HDL (C-based, industry-driven) oVHSIC HDL or VHDL (Ada-based, defense/industry/university-driven).

25. 1/16/2003 ECE 551 Spring 2003 25 How about HDLs Instead of Diagrams? - 2  Advantages of HDLs oHighly portable (text) oDescribes multiple levels of abstraction oRepresents parallelism oProvides many descriptive styles  Structural  Register Transfer Level (RTL)  Behavioral oServe as input for synthesis

26. 1/16/2003 ECE 551 Spring 2003 26 How about Synthesis instead of Manual Design?  Increased design efficiency  Reduces verification/validation problem  Ability to explore more of overall design space  Are there disadvantages?  Potential for better optimization

27. 1/16/2003 ECE 551 Spring 2003 27 HDL/Synthesis Design Flow - 1 Pre-Synthesis Sign-Off Verification: Functional Design Specification Design Partition Design Entry: HDL Behavioral Integration To next page Verification: Functional Synthesis and Technology Map

28. 1/16/2003 ECE 551 Spring 2003 28 HDL/Synthesis Design Flow - 2 Extract Parasitics Test Generation & Fault Simulation Verification: Post-Synthesis Timing Verification: Post-Synthesis Physical Design From prior page Verification: Physical & Electrical Design Sign-Off

29. 1/16/2003 ECE 551 Spring 2003 29 An Example from Industry  A G3 wireless processor was designed using the following methodology: oEntire processor modeled and tested using VHDL and C-based test programs oProcessor functionality verified by synthesizing to an FPGA and running 3G wireless applications at 25 MHz oProcessor timing and design feasibility verified by synthesizing to a standard cell library and running applications at 500 MHz. oFinal version of processor implemented using a mix of standard cell and custom logic to achieve low- power and 800 MHz clock speed.

30. 1/16/2003 ECE 551 Spring 2003 30 Newer Technologies and Design Flows - SOC  System-on-a-Chip (SoC) oDesigners use (Intellectual Property – IP) cores  RISC Core, DSP, Microcontroller, Memory  The main function is to glue many cores and generate/design only those components for which cores and designs may not be available  Used in ASIC as well as custom design environment  The issues relevant to this will be discussed near the end of the course

31. 1/16/2003 ECE 551 Spring 2003 31 Synthesis and Technology Map Contemporary Design Flow - 1 Pre-Synthesis Sign-Off Design Specification Design Partition Verification: Functional To HDL/Synth Design Flow -2 Integration & Verification: Functional Select IP Cores Design Entry: HDL Behavioral Preliminary Phys. Design

32. 1/16/2003 ECE 551 Spring 2003 32 Lecture 1.2 Summary  Application Specific Integrated Circuit (ASIC) Technologies oProvides a basis for what we will design  IC Costs oGives a basis for technology selection  ASIC Design Flows oShows the role of HDLs and synthesis oProvides a structure for  what we will learn  What we will do

33. 1/16/2003 ECE 551 Spring 2003 33 References 1) Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997.

34. 1/16/2003 ECE 551 Spring 2003 34 Lecture 1.3 Pragmatics 1  Pragmatics refers to practical design choices and techniques  Topics oCell Libraries oAsynchronous Circuits oThree-State Logic and Hi-Z State

35. 1/16/2003 ECE 551 Spring 2003 35 Cells and Cell Libraries  What is a cell?  What is a cell library?  What appears in the cell library for each ASIC cell?

36. 1/16/2003 ECE 551 Spring 2003 36 What is a Cell?  Cells are the building blocks for digital designs  Come in different sizes, shapes and functions varying from transistors to large memory arrays or even a processor  Typically cells: oSmall Scale: AND, OR, NAND, NOR, NOT, AOI, OAI, Flip-Flops, Latches oMedium Scale: Multiplexers, Decoders, Adders oLarge Scale: Memories, Processors  Provided by ASIC vendors

37. 1/16/2003 ECE 551 Spring 2003 37 What is a Cell Library?  A database specifying and describing the target technology in the form of pre- designed objects called cells. Synthesis target technology.  In-Class Discussion: What are typical components in the database for each cell?

38. 1/16/2003 ECE 551 Spring 2003 38 Asynchronous Techniques  Delay-dependent design  Combinational hazards  Combinational hazard prevention  Asynchronous design

39. 1/16/2003 ECE 551 Spring 2003 39 Delay-Dependent Design 1 LA PA A A LA PA Example: Level-to-Pulse Converter(Delay-Based)

40. 1/16/2003 ECE 551 Spring 2003 40 Delay-Dependent Design 2  Sometimes useful  But should be avoided  Time delays vary and so may: oFail oProduce variable results, e. g. pulse length

41. 1/16/2003 ECE 551 Spring 2003 41 Delay-Dependent Design 3 LA PA D QC Clock  Level on LA must be longer than a clock period and must not rise close to the positive clock edge. Ideally, synchronous with Clock.  Level to Pulse Converter (Synchronous)

42. 1/16/2003 ECE 551 Spring 2003 42 Combinational Hazards 1  Example - Hazard in a Multiplexer A C F B 1 1 B F

43. 1/16/2003 ECE 551 Spring 2003 43 Combinational Hazards - 2  A circuit has a hazard if there exists an assignment of delays such that an unwanted signal transition (glitch), can occur.  Types of changes on combinational circuit inputs : oSingle-input change (SIC) oMultiple-input change (MIC)  A SIC static hazard exists on a circuit output if in response to a SIC, the output momentarily changes to the opposite value. oStatic 1-hazard – output value to remain at 1 oStatic 0-hazard – output value to remain at 0

44. 1/16/2003 ECE 551 Spring 2003 44 Combinational Hazards - 3  Classification of Combinational Hazards oStatic – SIC/MIC – output changes when it should remain fixed - output value within the “transition region of input changes is fixed. oDynamic – SIC/MIC – output changes three or more times when it should change only once. oEssential – MIC – output changes when it should remain fixed – output value within the “transition region” of input changes not fixed.

45. 1/16/2003 ECE 551 Spring 2003 45 Combination Hazards - 4  In-class Example: Illustration of static, dynamic and essential hazards

46. 1/16/2003 ECE 551 Spring 2003 46 Combinational Hazards - 5  Consequences of Hazards oSignals with hazards within or entering asynchronous circuits (note that a flip-flop is an asynchronous circuit with respect to its clock signal!) oCause incorrect state behavior  Extra state changes  Incorrect state changes  In-Class Example: Prevention of Hazards oRedundant Logic oDelay Dependence

47. 1/16/2003 ECE 551 Spring 2003 47 Asynchronous Design - 1  Which of the following sequential circuits involve asynchronous design? oA circuit that has no global clock signal involved in its operation – state changes occur in response to input changes only. oA D flip-flop circuit oA circuit using clock gating on flip-flop clock inputs oA circuit with a clock which uses the clear and preset inputs on the flip-flops for other than initialization.

48. 1/16/2003 ECE 551 Spring 2003 48 Asynchronous Design - 2  Because of the difficulty of eliminating hazards, it is very difficult to insure correct operation under all timing possibilities  Design must be done manually or by use of very specialized synthesis tools.  Therefore, avoid it if you can!  If you truly need it, investigate some of the more contemporary approaches[1] which avoid some of the many difficulties.

49. 1/16/2003 ECE 551 Spring 2003 49 Three-State and Other Hi-Z States  Three-state conflicts  Floating three-state nets and inputs  Pull-ups and Pull-downs  Bus keepers

50. 1/16/2003 ECE 551 Spring 2003 50 Three-State Conflicts - 1  What are they and what are their effects? oStatic – Chip damage or static power consumption oDynamic – Dynamic or static power consumption 1 1 1 0 D0 D1 E0 E1 OUT E0 E1 E0 E1 1 1 1 1 0 0

51. 1/16/2003 ECE 551 Spring 2003 51 Three-State Conflicts - 2  How can conflicts be avoided? oStatic – Decoded enable signals oDynamic – Delay control 1 1 0 D0 D1 E0 E1 OUT E0 E1 E0 E1 1 1 0 1 0 0

52. 1/16/2003 ECE 551 Spring 2003 52 Floating Inputs and Three- State Nets - 1  Floating input values on gates can cause: ostatic power dissipation ohigh-frequency switching that induces power supply noise  Floating input values arise from: oGate inputs, e. g., for example on exterior of IC, that are not connected oLines driven by 3-state buffer or gate outputs, all of which are in the Hi-Z state.

53. 1/16/2003 ECE 551 Spring 2003 53 Floating Inputs and Three- State Nets – 2  How can floating inputs and nets be avoided? oUse a pull-up or pull-down resistor or transistor with a fixed gate voltage value.  Advantage – simple  Disadvantages – static power dissipation and loading of node oOn internal lines, particularly buses, use a bus keeper (weak buffer)

54. 1/16/2003 ECE 551 Spring 2003 54 Non-D flip-flops  D Flip-Flops oUnique characteristic – the typical master-slave DFF is also functionally an edge-triggered DFF.  Non- D Flip-Flops (JK, T, etc.) oIn the cell libraries, these flip-flop may be full-custom designs or may simply consist of a DFF with added logic. oIf it is just a DFF with added logic, you might as well design for a DFF to give the logic optimization software more flexibility.

55. 1/16/2003 ECE 551 Spring 2003 55 References [1] Chris J. Myers, Asynchronous Circuit Design, John Wiley & Sons, Inc., New York, 2001.