1. Chapter 1_4 Part II Counters

2. Overview Registers and load enable Register transfer operations
Part 1 - Registers, Microoperations and Implementations
Registers and load enable
Register transfer operations
Microoperations - arithmetic, logic, and shift
Microoperations on a single register
Multiplexer-based transfers
Shift registers
Part 2 - Counters, register cells, buses, & serial operations
Microoperations on single register (continued)
Counters
Register cell design
Multiplexer and bus-based transfers for multiple registers
Serial transfers and microoperations

3. Standard Graphic Symbols for Latch and Flip-Flops

5. Flip-Flop Characteristic Table

6. Flip-Flop Excitation Tables

7. Counters - Definition A counter is:
A register that “counts” through a specific sequence of states upon the application of a sequence of input pulses e.g. clock or other signals.
Counters can count up, count down, or count through other fixed sequences.

8. Binary Counter An n-bit binary counter: Consists of n flip-flops.
Counts from 0 to (2n -1).

9. Two Counter Categories
Synchronous counter
Ripple counters (Asynchronous counter)

10. … Counters Ripple Counters Synchronous counters
FF output transition serves as a source for triggering other FFs.
C input not triggered by the common clock pulse.
Synchronous counters
C inputs of all FFs receive the common clock pulse.
The change of state is determined from the present state of the counter.

11. Counter Examples Binary Counter Decade Counter Up-Down Counter
Arbitrary Sequence Counter
Johnson Counter
Ring Counter

12. Synchronous Counters

13. Synchronous Counters
The clk inputs of all flip-flops receive a common clock pulse (directly connected).
The change of state is determined from the present state.
By using combinational logic.

14. 4-bit Synchronous Binary Counter

15. Johnson Counter
The complement of the output of the last flip-flop is connected back to the input of the first flip-flop.
The counter will “fill up” with 1’s from left to right, and then will “fill up” with 0’s again

16. Figure 9–24 Timing sequence for a 4-bit Johnson counter.
Convert the waveform results into table form.
Thomas L. Floyd Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

17. Ring Counter
A “1” is always retained in the counter and simply shifted “around the ring”, advancing one stage for each clock pulse.

18. Output of 10-bit Ring Counter
Initial state is
Convert the waveform results into table form.

19. Johnson Counter vs Ring Counter

20. Asynchronous Counters

21. Ripple Counters – clk Source
The clk inputs of some flip-flops are supplied by the outputs on other flip-flops.
The (Master) CLOCK is connected to the clk input on the LSB bit flip-flop.
For all other bits, a flip-flop output is connected to the clock input,
Thus, the circuit is not synchronous.

22. Ripple Counters – Pros & Cons
Advantage
Simple Hardware (Decoder gates not required).
Low power consumption.
Disadvantage
Slow
Output change is delayed more for each bit towards the MSB.

23. 4-Bit Ripple Counter Both J and K inputs of the flip-flops are
tied to logic 1
flip-flop
complements

24. 5-4 Ripple Counters Figure 5-8
J and K of all FFs – tied together to logic 1
Negative edge triggered clock inputs.
Q0 serves as clock input to 2nd FF, and so on.
N(Clear) – clears registers to 0 asynchronously.

25. Design of Synchronous Binary Counters
Using D flip-fops
Using JK flip-flops

26. Counting Sequence of a 4-bit Binary Counter

27. 4-bit Binary Counter
Using D flip-flop

28. State Table and Flip-Flop Inputs for Binary Counter

29. What’s next? ..
K-maps (4)
Minimized Equations for: D0 D1 D2 D3

30. 4-Bit Binary Counter with D Flip-Flops

31. 4-bit Binary Counter
Using JK flip-flop

32. State Table and Flip-Flop Inputs for Binary Counter

33. K-Maps

34. Count-Enable Input To control the operation of counter, EN.
JQ0 = KQ0 = EN
JQ1 = KQ1 = Q0 . EN
JQ2 = KQ2 = Q0 . Q1 . EN
JQ3 = KQ3 = Q0 . Q1 . Q2 . EN
EN = 0; all J and K inputs equal to 0, FFs- no change.
EN = 1; JQ0 = KQ0 = 1, and the other equations follow Fig. 5-9.

35. 4-Bit Synchronous Binary Counter

36. Binary Counter with Parallel Load
Counters in digital systems, e.g. computers, often require a parallel-load capability.
To transfer an initial binary number into the counter before the count operation.
Load = 1; count operation disabled, data transferred from the 4 parallel inputs into the 4 FFs.
Load = 0 and Count = 1; normal operation.

37. 4-Bit Binary Counter with Parallel Load

38. Up-Down Binary Counter

39. Synchronous Count Down Counter
Sequence (reverse):
From 1111 to 0000 and back to 1111 to repeat the count.
The logic diagram is similar to the count-up counter, except that the inputs to the AND gates must come from the complement outputs of the flip-flops.

40. Synchronous Up-Down Counter
Needs a mode input to select between the two operations.
S=1: count up
S=0: count down
Also need a count enable input, EN:
EN=1; normal operation (up/down)
EN=0; disable both counts

41. 4-bit BCD Counter
Using T flip-flop

42. State Table and Flip-Flop Inputs for BCD Counter

43. The scHeMatiC Draw the K-maps and get the minimized equations.
.. Draw with four T flip-flops, four AND gates and one Or gate.

44. Arbitrary Sequence Counter
Using JK flip-flop

45. Counter with Arbitrary Count

46. State Table and Flip-Flop Inputs for Counter

47. Counter with Arbitrary Count

48. Question …
What does this mean:
“This counter is presettable…” ?