HardWireTM FpgASIC The Superior ASIC Solution CORES

Application Engineering Mission Help our customers with faster time to market and flexible product life cycle management through programmable logic solutions of software, application engineering and silicon Silicon Software Application Engineering

ASIC Alternatives Xilinx Product Line Custom Highest Density ASIC Tools ASIC Xilinx Product Line Custom Transparent Conversion 100% Tested FpgASIC Programmable GA Architecture High Density ASIC Tools FPGA Programmable PAL Architecture Medium Density PAL-like Tools CPLD Programmable AND/OR Architecture Low Density Simple Tools PAL™

FPGA Technology Roadmap Next Generation Up to 400k logic gates 0.25/0.18  XC4000XV Largest Device Density/Performance XC40250XV 0.25  m XC4000XL 2.5 Volt Power Supply Largest Device 30% Faster than XL XC4085XL XC4000EX 0.35  m Largest Device 3.3 Volt Power Supply 2.0M gates XC4000E XC4036EX 2.0M gates 30% faster than EX (175K logic cells) Largest Device 0.5  m (175K logic cells) XC4025E 5 Volt Power Supply in the year in the year 0.5  m 30% faster than E 2001 2001 5 Volt Power Supply 1995 1996 1997 1998 1999 Year

FPGA Design Advantages ASIC Test Vector Generation 40% Reduced Simulation Requirements Hardware Verification Concurrent Development of System Hardware and Software Highly Flexible No Test Vector Generation No Prototype or Re-spin Leadtime Test Vector Generation 40% Simulation 25% Schematic Capture 10% Prototype Test 10% Vendor Interface 10% Specifications - 5% ASIC Design Time by Task * Source: Integrated Circuit Engineering Corporation, 1996

The Xilinx Advantage “Design-Once” FpgASIC Conversion HardWire ASIC FPGA Design FpgASIC Fast Development Time-to-Market Concurrent Engineering Flexibility No Customer Re-design No Customer Vectors All FPGA Features Mask Programmed Pricing Fastest Time from Design Concept to Low-cost Silicon

Typical Product Life Cycle Model Design and prototype with FPGA Production ramp in FPGA during FpgASIC conversion FPGA for production upsides and system E-O-L UNPLANNED UPSIDE PRODUCTION RAMP-UP PROGRAMMABLE VOLUME VOLUME END-OF-LIFE HardWiire FpgASIC

Xilinx FPGA + FpgASIC Advantage “Design Once” Powerful Unique Xilinx Logic Methodology Logic Design FPGA Implementation FPGA ASIC Implementation “Make” Non-Turn-key “Buy” Turn-Key FpgaASIC Implementation Option FpgASIC ASIC Xilinx Holds the Patent on “FPGA Conversion Without Re-Design”

HardWire FpgASIC Technology Roadmap XH4 0.25/ 0.18Technology FPGA-specific Architecture High Performance/Embedded Cores Advanced Mapping XH3 0.5/ 0.35 Technology First FpgASIC High performance/Size-optimized ASIC Core “DesignLock 3” HW2 0.6Technology Sea of Gates Architecture (S.O.G.) Die Size Optimized “DesignLockTM” Conversion Methodology HW1 0.8 Technology FPGA Replica Single Mask Personalization “Direct-Map” Conversion 1992 1994 1997 1998 1999

Xilinx Introduces the FpgASIC XH3 HardWire ASIC Family Built in Xilinx Features Package Optimized Die Sizes Same Proven DESIGNLOCK Flow Performance Optimized for Xilinx FPGA’s Competitive With Commercial ASIC’s What it says! 13

XH3 Family Product Support DEVICE XH302 XH304 XH306 XH308 XH310 XH312 DLM USABLE 14,000 25,000 45,000 70,000 90,000 140,000 GATES MAX PADS 136 172 204 240 292 352 PACKAGES PC84 TQ144 PQ160 PQ240 PQ240 SUPPORTED PC84 PQ100 PQ208 BG225 BG225 PQ304 PQ100 TQ100 BG256 BG256 BG352 TQ100 VQ100 HQ304 BG432 VQ100 TQ144 BG352 PQ160 E/EX XC4005 XC4010 XC4013 XC4020 XC4025 XC4028 FPGAs XC4008 XC4013 XC4020 XC4025 XC4028 XC4036 SUPPORTED XC4010 XC4025 XC4028 XC4036 XC4013

FPGA + HardWire FpgASIC The Superior ASIC Solution Benefit ASIC Alternative Flexible Development with FPGA Quickly respond to market requirements Delays for redesign Working silicon at design start with FPGA Early system verification and rapid prototype Can use only simulation to verify design Cost-effective early production device Off-the-shelf availability with no NRE commitment Inventory risk, minimum order qty Turn-key conversion to HardWire FpgASIC Little engineering requirement for cost- reduction Need test vector development by design engineering

HardWire FpgASIC Roadmap * 1st Production submittals

FpgASIC Differentiation vs. ASIC Key Differentiator Customer Benefit DesignLock™  No verification/simulation Same I/O as FPGA Same start-up timing Same RAM as FPGA No test vectors to write FpgASIC Architecture FPGA Compatibility Turn-key Conversion No customer resources

Summary FPGA FpgASIC CORES Result: Superior Time-To-Volume Increased demand for ASIC HardWire ASIC best solution Essential for selling hi-density FPGAs Faster, Denser FPGA FpgASIC CORES Design Trend Result: Superior Time-To-Volume