C. Beigbeder Final design Review ECAL/HCAL Frond End  FE board : current prototype  Test results Qualification Clock adjustment Noise analysis  FE board : Final version Evolution Planning  Production tests Takaya and/or boundary scan Single board test to full-crate test Software aspects  Questions

Final Design Review Sept 2005 The FE board in the FE crate. 250 boards including spares will be produced mm 280mm 25 x ‘9U‘ Crates

Final Design Review Sept 2005 Block diagram of the FE board. Block diagram of the FE board.

Final Design Review Sept 2005 Calorimeter FE board.

Final Design Review Sept 2005 Details Delay lines Analog chip ADC Delay chip FE_Pga Trig_PGA Seq_Pga Glue_Pga Serializers + Deserializers Rad-hard regulators Clock Receiver/drivers Analog input connectors Jtagconnector Lemo(Probes)

Final Design Review Sept 2005 A zoom on the socket … Home-made socket : FPGA BGA contact through golden foam ( no soldering needed)

Final Design Review Sept 2005 ECAL/HCAL FE CARD WITH 2 FEPGA 1 SEQPGA 1 GLUE PGA for ECS on sockets.

Final Design Review Sept 2005 Analog part meters ( same for all ) On-detector clipping Delay line Buffer Cable effect cancellation Pedestal adjustment to ~128bins

Final Design Review Sept 2005 Delay Chip Technology : AMS 0.8µm pure CMOS process in a 28 pin SOZ package Half of the production has already been tested : yield is about 95%. The power consumption is about The linearity is better than +/- 100ps per step. The clock jitter is less than 15ps RMS for all channels. http………

Final Design Review Sept 2005 Fe PGA

Final Design Review Sept 2005 Actel Axcelerator Match our needs in term of : Radiation tolerance & Latch up Match our needs in term of : Radiation tolerance & Latch up Nb of IO pins, nb of cells Nb of IO pins, nb of cells Nb of Ram blocks for Latency and Spy Nb of Ram blocks for Latency and Spy …. And price : Ax 250 = 39,5 € Ax 500 = 62,3 € + 2 € ( for programmation ) Ax 500 = 62,3 € + 2 € ( for programmation )

Final Design Review Sept 2005 ADC data processing Clock adjustment study : see next talk Analysis of the 2 methods : see next talk

Final Design Review Sept 2005 Front-end PGAs.

Final Design Review Sept 2005 Processing and format Processing and format BX - IdL0 - Id Parity PRS/SPD Calib. Test Seq. PRS/SPD Channel 8 Channel 4 Channel 0 Header Separator Trailer(VerticalParity) Channel 31 [É] 0É 0É É0 É Parity Data ECAL/HCALTrigger ECAL/HCAL Parity Line i  Channel 4x ( ( i - 1 ) modulo 8 ) + int ( ( iĞ 1 ) / 8 ) Line 1 É

Final Design Review Sept 2005 SeqPGA : sequencer part Fe data Header Trailor 2 words = to zero as separator

Final Design Review Sept 2005 Triple voting FIFO (derandomizer)

Final Design Review Sept 2005 Glue PGA

Final Design Review Sept 2005 L0 calorimeter trigger

Final Design Review Sept 2005 TrigPGA : block diagram

Final Design Review Sept 2005 TrigPGA : mapping

Final Design Review Sept 2005 TrigPGA : internal latency

Final Design Review Sept 2005 Clock distribution Multi-drop analysis Unidirectionnal multi-load analysis

Final Design Review Sept 2005 Power distribution Board Consumption : +5 V = 4A +3.3V = 2 A -5V = 1 A

Final Design Review Sept 2005 FE board : new version   SeqPGA and Glue in ProAsic 300 and 150. New version of ProAsic has been qualified by Actel and NASA and matches our requirements. Time schedule makes very difficult a complete change of all PGAs : Only PGAs interfacing with the board’s outside are changed : Seq and Glue. But TrigPGA would thus have to be redesigned because of the lower performance of the ProAsic. ProAsic 150 = 30 € ProAsic300 = 66 € ProAsic 300 = 66 €

Final Design Review Sept 2005 FE board : new version   New design of the analog input part : Analog test signals will be routed carefully within the ground plane. F125 located closer to the shaper.   New version of the handshake FePGA-SeqPGA. Depending on future noise analysis results, the 8 FePGA may send data one after the other instead of all together. Current peak may thus be avoided.   Evolution of the connectors. Use of another AB type connector on the 6U backplane (see Daniel’s talk).

Final Design Review Sept 2005 Programming-debugging : JTAG Chain

Final Design Review Sept 2005 Production   Manufacturer will perform an aging of 16 boards in the same crate. Goal : Detection of bad soldered components.   Boundary Scan: Ability to drive 2 chains independently. GluePGA has to be programmed first. Test of Actels’ interconnections.   ‘ Takaya ‘ test : Impedance value and interconnection. Bad soldered chips with ‘open checker’. Needs a plug to test connectors. Footprints for probes have to be foreseen.

Final Design Review Sept 2005 Final layout Thickness : 2.4 mm. Thickness : 2.4 mm. 12 layers 12 layers Minimum isolation : 0.11mm Minimum isolation : 0.11mm Via : width = 0.35 mm Via : width = 0.35 mm Plating : Ni-Au for BGAs Plating : Ni-Au for BGAs 2845 components 2845 components 3464 nets 3464 nets pins pins ~10000 connections ~10000 connections 6072 vias 6072 vias

Final Design Review Sept 2005 Some layers …

Final Design Review Sept 2005 FE board production schedule.  Public call for tender February 15th ( Yes !!! ). => May 1 st ( 51days + 4 weeks) : notification.  June 10 th : arrival of the two first boards ( 5 weeks ) => 7 weeks for the thorough test.  July 27 th : decision based on the boards’ characterization Not OK => two new prototypes ( 4 weeks + 3 weeks test + holidays) OK => 16 boards to equip a full crate : ( 3 weeks + holidays)  October 7 th : beginning of production.  Mid November : 40% of production.  End of December : end of production.  November to June : Reception test  Installation : from December 2005 to July 2006 ( together with CROC and Crate).