1. Tests Front-end card Status
Test Front-end board
Test board architecture.
Test bench.
Firmware architecture
DAQ Idea
Status of the firmware Block
Test
Firmware blocks
LHCb upgrade meeting

2. Tests board architecture
Schedule for SPECS development
Board size : 305 mm x 155 mm 10 layers
IN / OUT (NIM)
USB
Delay Chip
SPEC
Mezzanine
A3PE1500
REGULATORS
AX500
Analog
Mezzanine
120mm x 120mm
"LAL Support"
for AX 500
LHCb upgrade meeting
October 5th 2010

3. Test bench
LHCb upgrade meeting
October 5th 2010

4. Firmware architecture (in A3PE1500)
CROC prototype tests : schedule
Schedule for SPECS development
All Blocks inside A3PE1500 in Verilog language
USB / I2C module
I2C1
Delay chip LAL
(x3)
USB / I2C module
I2C2
Delay chip CERN
(x3)
USB / I2C module
I2C3
AX500 FPGA
USB / I2C module
I2C4
Analog mezzanine
USB
Interface
Step 1 : used the board with power supply and clock Ctrl
Status Register
Tests register
16/32 bits Rd/Wr
Reset Register
Step 2 : Add trigger and Delay Chip Ctrl
Ctrl Register
Step 3 : Add data processing and DAQ
In Ext Clk
Global Clk
(Diff 40 Mhz)
Clock
Ctrl
USB Clk
(10 Mhz)
Q : 40 Mhz
SPECS Clk
Out Ext Clk
Trigger System
Data FIFO/RAM
Clock Divider
ADC Data
Test value injection
ADC Data processing
Re-synchronize ADC Input
Dynamique pedestral subtraction
Version : 02/01/ :11
LHCb upgrade meeting
October 5th 2010

5. DAQ Idea … Inside A3PE1500 For DAQ DAQ sequence 60 blocks of 4608 Bit
12 x 3 Blocks RAM to ADC data FIFO
2 Blocks RAM to enable ADC data
Ctrl_Register (16b) 1
Start acquisition
(ADC running)
DAQ sequence
Load RAM sequence
USB Interface write the start_acquisition bit in the Ctrl_Register
ADC running
ADC data are writing in FIFO
When the FIFO is full we write FIFO_full bit in the Status_register
The PC scrutinize the status register and when the FIFO_full bit is high the USB read the FIFO
When the FIFO is empty we can start new acquisition
USB
Interface
FIFO
(18 x 768)
To One ADC Channel 12
ADC Data input
FIFO Empty
3 x RAMBlock
of 18 x 256
FIFO Full PC 1
Status_Register (16b)
Enable ADC
RAM / FIFO Block
for all channels 8
O_Enable ADC Channels
or NIM connector
(8 x 768)
A3PE Firmware
LHCb upgrade meeting
October 5th 2010

6. Tests Status Download A3PE1500 with FlashPro 4
(Problem solved)
Rd / Wr register by USB inside A3P
Used “test_245” by Chafik
Tests with 16 and 32 bits Rd/Wr register inside A3PE1500
Rd / Wr Status, Ctrl, Reset register and clock ctrl implementation
Two board available (one tested)
(One for Carlos TestBench) ok ok
to do ok
October 5th 2010

7. Status of the firmware blocks
All Blocks inside A3PE1500 in Verilog language
Clock divider and trigger generator module for Lemo outputs (to adapt from the CROC by Olivier)
I2C Module (to adapt from Jihane’s code by Olivier)
Processing ADC data (in progress by Christophe)
Data storage (to do by Jimmy)
Test value injection RAM (to do by Jimmy)
Step 2
Step 2
Step 3
Step 3
Step 3
LHCb upgrade meeting
October 5th 2010

8. SPARE
LHCb upgrade meeting

9. SPARE
LHCb upgrade meeting

10. SPARE
LHCb upgrade meeting

11. SPARE
LHCb upgrade meeting

12. Tests board power supply
CROC prototype tests : schedule
Schedule for SPECS development
P7V
Regulator
AVCC_1 for Analog Mezza (+3 to +5V)
Regulator
AVCC_2 for Analog Mezza (+3 to +5V)
Regulator
DVDD for Analog Mezza (+2V5 to +3V3)
Regulator
VCC for board (+5V)
Regulator
P3V3 for board (+3,3v)
(VccIO bank fixe)
Regulator
P1V5 for FPGA core
Regulator
1,5v < VccIOB_Var < +2,5v)
(VccIO bank variable)
Regulator
P2V5 for bank (+2,5v)
(VccIO bank LVDS)
M7V
Regulator
AVEE for Analog Mezza (-3 to -5V)
Regulator
VEE for board (-5V) {NIM translators}
Lab. Power Supply input (+/- 7V)
10 Radiation tolerance regulators ! !
LHCb upgrade meeting

13. CROC prototype tests : schedule Schedule for SPECS development
Tests board Clock Tree
CROC prototype tests : schedule
Schedule for SPECS development
Each FPGA receive 2 adjustable Clock (LVDS)
Analog mezzanine receive also 2 adjustable Clock (LVDS)
Each ADC_Channel receive 1 Clock (LVDS)
LHCb upgrade meeting

14. A3PE firmware blocks : USB interface module
USB Interface standard module
I2C modules (x4)
FT245 side
User side
USB / I2C
module
Sda
Delay chip
LAL
Scl
SubAdd[6..0]
(x3)
USB_Data[7..0]
USB Interface
Standard module
UserData[7..0]
RXF
USB / I2C
module
Sda
Delay chip
CERN
N_Write
Scl RD
(x3)
N_Read
TXE
N_Sync
USB / I2C
module
Sda
AX500 WR
Scl
Interrupt
Clk
USB / I2C
module
Sda
N_Reset
Analog
mezzanine
Scl
LHCb upgrade meeting

15. A3PE firmware blocks : Clock divider and trigger generator
50 ns to 0.4s (24 bits counter)
Internal Trigger
With this module we can produce trigger (external trigger or software command)
Tdelay (8bits)
TL0 (16 bits)
Registers loaded by USB or SPECS :
Registers loaded by USB or SPECS :
Ndump (8bits)
Nspy (8 bits)
LHCb upgrade meeting

16. A3PE firmware blocks : data processing
Processing ADC data
Re-synchronize ADC input
Dynamique pedestal subtraction
Suppression of low frequency noise
Trigger processing
Convert ADC data to 8 bit
Sent towards the TRIG-PGA
AX500?
RAM block
8 x 16 x 256
LHCb upgrade meeting

17. A3PE firmware blocks : RAM
Data storage (output buffer) before readout
8 x 16 (12 used) x 256
Read only by USB (first !)
Test value injection RAM
Use of the RAM test describ in LHCb ECAL/ HCAL Front-End card
There exist different ways to use the RAM test:
- The standard one: the RAM address is increased every 25ns by the clock and the sequence of 256 addresses is initiated by the test-sequence signal, originating in the calibration command of the channel B and enabled by the corresponding status of an I2C register. The sequence ends up after 256 clock cycles.
- A variant with an enable loop bit loaded by I2C. In this case after the sequence initialisation the RAM address counter continues advancing and jumps automatically from address 255 to address 0.
- The L0 mode where the RAM address is incremented upon reception of each L0. The sequence can be terminated at 255 or looped as in case 2.
- Calibration mode where the RAM address is incremented upon reception of test sequence command. In this case by definition the system will loop after address 255.
LHCb upgrade meeting