1. 1 Outer Tracker Front-End Layout Distribution of Signals and Bias NIKHEF/HeidelbergOctober 2002

2. 2 Assumptions about OTR Configuration Three identical tracking stations (ST1, ST2, ST3) of four planes (XVVX) of straw tube modules. For the distribution of TFC, I2C, and bias, tentatively we propose to subdivide each station in four quadrants. Each quadrant needs services for four planes, each one consisting of eight 340mm-wide (2 x 64 wires) straw modules and one 170mm-wide (2 x 32 wires) straw module. The distribution of services is the task of the Tracker Quadrant Distribution Box (TQ Distribox). The TQ Distribox fulfills the following functions: –Distributes the timing and trigger signals (TFC) –Receives and distributes the slow control signals (ECS) –Act as patch panel for the power (High Voltage and Low Voltage)

3. 3 Why 4 Quadrants? Mechanical constraints: –Must be able to open station in two halves independantly without disconnecting cables  distribution boxes must be solidal to half station. Timing constraints: –Module to module clock-phase differences < 1 ns  limit max cable length (half station length ~ 3 M = 15 ns). Electrical constraints: –Minimize ground loops, mount distribution box on detector frame.

4. 4 Detector Layout

5. 5 Module Front-End The details of control and power distribution depend on the implementation of the FE electronics and the interconnection between FE boards. –The main parts of the Module FE are: ASDBLR chips, OTIS TDCs, GOL and ADC. TFC : –Clock  OTIS, GOL –BC Reset  OTIS –L0 Reset  OTIS,GOL –L0 Trigger  OTIS –Test Pulse  ASDBLR ECS: I2C  OTIS, GOL (ADC, TTCrx may be in TQ Distribox) (JTAG  ADC, may be in TQ Distribox) LV: –-3 V  ASDBLR –+3 V  ASDBLR, (ADC) –+2.5 V  OTIS, GOL, (ADC) HV: –HV  HV boards

6. 6 Signals To Distribute TFC: 4 planes x 9 FE-boxes  36 CAT5 cables –The OTIS has one fast reset, the TFC signals are: Bunch Clock, L0 Trigger, Reset and Testpulse. To distribute these signals CAT5 cable can be used (max. 4 differential signals). If in a later version of the OTIS a separate Bunch Count Reset and L0 Reset are used, the resets could be coded, because it is preferred to use CAT5 cable instead of flatcable to distribute the TFC signals. LV: 4 planes x 9 FE-boxes/planes  36 LV cables –4 wires: +5V, Return, -5V, Return I2C: 4 planes x 1 or 2 daisy chain/plane –dependant on ADC type Monitor signals: 4 planes x 9 FE-boxes  36 cables –Temperature, +3V, -3V, 2.5V

7. 7 TQ Distribution Box

8. 8 Module FE-box Layout Contains: –16 ASDBLR –4 OTIS –1 GOL –(1 ADC) One board per plane : –obvious! One style board: –Not enough space between planes of a station –We have anyway a number of half-modules Chip waste: –Not more than 1 OTIS per board –OTIS and ASDBLR separated –Not more then 2 ASDBLR per board

9. 9 Proposal For ASDBLR / OTIS Board(s)

10. 10 Signal and Voltage Distribution Scenarios Separate GOL and AUX boards Integrated GOL and AUX boards

11. 11 How Could an Integrated AUX/GOL Board Look Like? Remember that in the task division: AUX Board assigned to NIKHEF (considered as part of FE) GOL Board assigned to HD/Dresden (considered as part of L1) task division will not be altered HD will design the GOL part, while NIKHEF the rest NIKHEF will integrate the two designs in the final layout NIKHEF will provide enough geometry/connectors specs to HD such that HD design will resemble final layout as closely as possible An integrated AUX/GOL board is possible without conflict

12. 12 Front-End Layout On “Wide” Detector Module OTIS GOL ASDBLR OTIS ASDBLR HV board

13. 13 Front-End Layout On “Narrow” Detector Module OTIS GOL ASDBLR HV board

14. 14 Nota Bene The GOL/ADC board is about 120 mm wide, together with gas, high voltage and mechanical support it must fit in the 170 mm module. The OTIS board are in two types (left and right), according to where the GOL connector is, in order to avoid the use of cable in the module. The OTIS and ASDBLR chips are in one plane, so they can be cooled by the case of the module-box. Special care must be taken to ensure the cooling of the LV-regulators portion of the GOL/ADC board. As no cable is used to connect the OTIS data to the GOL the signals can be LVTTL, but LVDS is preferred (LVDS receivers needed for the GOL). LVDS repeaters needed to distribute TFC signals. I2C signals can be distributed using standard telephone cable and connectors (RJ11). We propose to have separate I2C bus lines for the control of the chips and for parameter monitoring.

15. 15 Signal And Power Connections From TQ Distribox to FE

16. 16 Details of TFC Distribution TTCrx decoding in TQ Distribox –See LHCb 2001-017 TFC Broadcast Format Reset decoding in Front-end Module –Needed to enable the distribution of 5 TFC signals via CAT5 cable Distribution of TFC signals –Do we need LVDS repeaters in the Front-end Module?

17. 17 TTCrx Decoding BC-Reset Test-PulseL0-Reset Clock Brcst(0) Brcst(7:2) Reset 01xx01 0001xx Test-Pulse

18. 18 Reset Decoding BC-Reset L0-Reset Clock Reset Both decoding schemes in one Actel antifuse FPGA

19. 19 Distribution of TFC signals without LVDS repeaters GOL OTIS 100 VCC 4 meter 15 cm stubs LVDS driver Distribox GOL board 4 OTIS boards Power Supply Jitter ~ 70 ps Max phase difference between OTIS < 400 ps

20. 20 Distribution of TFC signals with LVDS repeaters GOL OTIS VCC 4 meter LVDS driver Distribox GOL board 4 OTIS boards Power Supply LVDS repeater Jitter ~ 50 ps Phase difference between OTIS < 200 ps

21. 21 Conclusions on TFC Signal Distribution  TFC Signals can be distributed without the use of an LVDS repeater in the Front-end box  No significant increase of the jitter (50 ps > 70 ps)  Less components needed: cheaper, less dissipation  No extra propagation delay  Phase difference between OTIS chips is a bit higher <400 ps compared to < 200 ps  Higher demands on board layout