1. CSC Muon Sorter M. Matveev Rice University January 7, 2003

2. VME J1 BACKPLANE CUSTOM BACKPLANE 9U * 400 MM BOARD SCSI-3 CONNECTORS LVDS DRIVERS CCB INTERFACE SORTER LOGIC INPUT AND OUTPUT FIFO BUFFERS VME/JTAG INTERFACE SP1 SP12 SP3 SP10 SP5 SP8 SP6 SP7 SP4 SP9 SP2 SP11 Muon Sorter Block Diagram CABLES TO GLOBAL MUON TRIGGER CRATE GTLP TRANSCEIVERS MEZZANINE CARD CCB WINNERS 1st 2nd 3rd 4th Xilinx XC2V4000

3. FPGA Design Comprises: - Sorter “4 out of 36” based on 7-bit Rank - Output LUT - 12 Input and 4 output 32-bit FIFO buffers (255-bit deep) - “Winner” logic - CCB interface - VME interface (A24D16 slave + Geographical Address) Based on Xilinx XC2V4000-5FF1152C (~60% of FPGA resources are used, ~50Mhz performance using ISE 5.1.03i XST Synthesis) Ghost cancellation logic is not included Latency – 132 ns - Input latching @ 80MHz and demultiplexing - 1.0 BX - Sorting “4 out of 36” and output data merging - 2.5 BX (reduced from 3.0) - LUT conversion - 1.0 BX - Output data latching - 0.5 BX - GTLP-to-LVTTL and LVTTL-to-LVDS conversion - 6 ns

4. Muon Sorter Output Data Conversion Rank[6..0] VC A[6..0] A[7] D[4..0] D[7..5] Pt_GMT[4..0] Quality_GMT[2..0] Phi_SP[4..0] SP_ID[3..0] A[4..0] A[8..5] D[7..0] Phi_GMT[7..0] LUT 256x8 1 muon out of 4 LUT 512x8 Eta_SP[4..0] SP_ID[3..0] Decoder Eta_GMT[5..0]

5. QU2QU1QU0Pt4Pt3Pt2Pt1Pt0Phi7Phi6Phi5Phi4Phi3Phi2Phi1Phi0 15 14131211109654321078 GND SEBC0BX2BX1BX0VC SHLEta5Eta4Eta3Eta2Eta1Eta0 31302928272625222120191817162324 MS-to-GMT Data Format 32 bits @ 40MHz per each muon CLK

6. SP Interface Data format, backplane and FPGA pin assignment are completely defined 28 SN74GTLPH16912 transceivers and 50 terminator resistor networks will be placed on both sides of the board GMT Interface Data format completely defined Need to finalize the connector part number. Pin assignment done SN74LVDS386/387 LVDS chipset JTAG Interface JTAG Access to Xilinx XC2V4000 FPGA - From VME using Fairchild SCANPSC100FSC JTAG controller - Xilinx Parallel Cable 4 (14-pin connector) JTAG Access to Xilinx XCR3128 PLD (VME control logic for SCANPSC100) - Xilinx Parallel Cable 4 (separate 14-pin connector)

7. Front Panel (single width) Four 68-pin SCSI-3 connectors (64 mm long each) 17 small LEDs - 4 winner muons sent to GMT - DTACK - JTAG access to FPGA from VME - FPGA configuration done - Test/Trigger Mode - Input/Output FIFO status (full/empty) - power +5V, +3.3V, +1.5V status - 1 reserved

8. MS Preliminary Cost Estimate PCB Routing - $8K PCB Fabrication (3 boards) - $3K PCB Assembly (3 boards) - $1K Components - $3K per board * Mezzanine card fabrication and assembly - $1K per board Total for 3 boards - $24K ($20K) * Mainly FPGA. Have 2 free FPGA (donation from Xilinx)

9. Muon Sorter Design Status and Plans Orcad schematic is completed (54 small chips, mostly drivers and receivers). The board is unpopulated, but routing will be complex due to mezzanine connections. 670 out of 782 mezzanine i/o are used. Updated specification is available on the web FPGA and PLD initial designs done (Xilinx Foundation ISE 5.1.03) Have most components in hand (excluding mezzanine connectors and assembled mezzanine cards) Ordered 9U Wiener crate. Expect by the end of January Ready to start PCB layout (outside vendor) - January…February – layout and fabrication (3 boards) - March…May – assembly and testing