1. 1 Calorimeter electronics Upgrade Outcome of the meeting that took place at LAL on March 9th, 2009 Calorimeter Upgrade Meeting Barcelona March 10th-11st, 2009

2. 2 Frédéric Machefert - Calorimeter Commissioning Meeting FPGA : AX or PA3 ? (I)‏ Two problems have been observed with the APA FPGA When two many bits flip altogether and quickly, the signals seen after the input buffers of the FPGA are corrupted. This is hardly documented by the manufacturers and the acceptable limits (number of bits flipping, average rate) depend on the implementation. When sending several bits on the FPGA inputs, the internal sampling of the signals by a unique external clock (and in spite of the usage of a dedicated clock tree) seems to be done with phase shifted clocks among the registers. This makes « synchronized » sampling of fast signals more difficult. It seems that we need to perform our own tests in order to find and be persuaded of the “good” solution. Two ways of testing the FPGA have been thought of : Having a prototype dedicated specifically to that problem, Using the FE-prototype to test the FPGA capabilities. It appeared that the second way is not favoured as it would increase the complexity of the design of the FE-prototype both in term of PCB and firmware.

3. 3 Frédéric Machefert - Calorimeter Commissioning Meeting FPGA : AX or PA3 ? (I)‏ Hence, we think that two prototypes have to be made. A first prototype to study the performances of the components. The second prototype would integrate a digital readout of the analog signals and be the FE-prototype. This means that the latter would be delayed in time as the first conclusions on the former need to be obtained. ProAsic3 seems to be easier to use (reprogrammable) and would be the baseline. Still, we may imagine that it cannot cope the signals exchanged. The AX would be the backup solution. But, we also have to prove that the AX may work. On the present front-end board we benefited a lot from the Silicon Explorer to debug the firmware. This does not exist on the APA. It seems that something similar exists on the ProAsic3 (Olivier). The following questions were raised : Price of this system, Resources needed to make it work.

4. 4 Frédéric Machefert - Calorimeter Commissioning Meeting First Prototype (I)‏ The first prototype would include A ProAsic3 A socket to receive an AX The possibility to exchange data Between the AX and the APA From an FPGA to itself A SPECS mezzanine connector A digital readout connector : the possibility to perform a readout of the digital implementation was thought of at this level. We imagined to have a connector on our prototype and be able to connect a mezzanine having the analog part up to after the ADC. This would help in checking that the readout may be performed with the FPGA chosen and may help in having an early and simple readout for Barcelona. The GBT standard is not well adapted to the FPGA outputs. We have to design a system to make the FPGA and GBT compatible. This system should be tested on this first prototype. If the FPGA-GBT link is mono-polar, a simple tension divisor was imagined (Jacques) but this would increase the overall consumption (back of the envelop calculation ~ 1A/80 outputs). The problem is more acute if we want to have differential outputs (and use the high speed capabilities of the GBT). NB : the FPGA bit flip problem was linked to the I/O current.

5. 5 Frédéric Machefert - Calorimeter Commissioning Meeting First Prototype (I) – Second Prototype We probably have to plan an interface with the analog mezzanine if this capability is confirmed : clock, SPECS, etc... ? Two reception areas for two delay chips. Only one would be connected at a time but we would have the possibility to solder either a Delay25 (CERN) or a LAL delay chip. This board would be used « on the table », powered with test bench power supplies. The difficulties experienced with the i 2 c and FPGAs lead to the test of the transactions with the FPGA on the prototype already. Despite of the usage of more links, a parallel bus seems simpler, safer, faster. The possibility to use the first prototype for irradiation tests was mentioned. But the conditions and purpose of those tests have to be defined precisely. The second Prototype would use : The components tested with the first one No component testing with this board The futur trigger implementation was supposed to be identical to the present one. This has to be confirmed but seemed clear to us. The question of integrating it to the second prototype was raised.