Xilinx Programmable Logic Development Systems Alliance Series version 3

® Award Winning Design Solutions  The industry’s fastest runtimes —2 to 10X faster than the competition  The industry’s highest performance —15 to 25 % faster clock rates than the competition  The industry’s leading devices —V2600E and V3200E, V405EM and V812EM, 2S200, Virtex-II  The industry’s most powerful design flows —Fast and efficient design methodologies for up to 10Million gates  The industry’s most productive partnerships —Partners with Over 30 of the industry’s most successful companies

® The Industry’s Fastest Runtimes Deliver the Fastest Time To Market  Ultra fast place and route runtimes —XCV100: 3-5 minutes (100,000 system gates) —XCV1000: minutes (1 M system gates!) —Real PCI design 64/66 in XCV300: ~ 5 minutes –Consumes ~ 12% of XCV300 BG432  Even faster than our previous release —From 10% to 100% for < 1 M gates —From 2X to 10X for > 1 M gates Runtime

®  Clock speeds >160MHz when targeting Virtex-E  I/O performance >622 Mbps when targeting Virtex-E  For existing designs, performance will increase by 10% to 15% from place and route algorithm improvements —Approximately a speed grade —For Virtex, Virtex-E, Spartan-II devices only The Industry’s Best Performance Accelerating Time To Market Performance

® The Industry’s Leading Devices  Extending the lead with Virtex-E —V2600E and V3200E  Unequalled memory and logic with the Extended Memory (EM) family —V405EM and V812EM  Awesome value for high-volume applications —The new Spartan-II family 2S200 device  Reinventing the FPGA, again with Virtex-II Device Technology

® The Industry’s Most Powerful Design Flows  Incremental synthesis / layout with high-level floorplanning  Efficient methodology for teams using modular design  Advanced debug capabilities using ChipScope ILA  Powerful HDL source archive; efficiently manages all design files Design Flows

® High-Level Floorplanning Enables Incremental Synthesis  Accelerates your time-to- market  Unchanged hierarchical blocks easily guided  Preserves timing for blocks unaffected by HDL design changes  Accelerates timing closure for complete design  Accelerates your time-to- market  Unchanged hierarchical blocks easily guided  Preserves timing for blocks unaffected by HDL design changes  Accelerates timing closure for complete design Industry First PCI uProcessor USB Ctrl Top Level HDL Floorplan defines layout area of each HDL blocks logic

® How High-Level Floorplanning Works  Incremental synthesis limits the name and logic changes to a single block instead of an entire design Top Block BBlock A  Xilinx high-level floorplanning isolates the place and route task to the area of the design that has changed and maintains timing of unchanged hierarchical blocks Result: Guide easily restores unchanged blocks in the design! Guide sees this: Instead of this: Block DBlock C

® Xilinx Modular Design Design Flow  Define modules In HDL block diagram  Floorplan area for each design module  Design, synthesize, place and route, and verify each module independently  Run global routing to interconnect modules Industry First

® Xilinx Modular Design Enabling Autonomous Team Design  Improves high-density design flows —Faster time-to-market by enabling multiple designers to work on the design of a single device —Changes task from high-density device design to high-performance module design  Improves high-density design performance —Enables more accurate / aggressive timing estimates during synthesis! —Guaranteed module timing  Enables a more robust incremental design flow —Changes in HDL are retained within a module

® The ChipScope ILA System Control USER FUNCTION ILA USER FUNCTION USER FUNCTION ILA Chipscope ILA MultiLINX PC with ChipScope MultiLINX Cable JTAG Connection Target Board Target FPGA with up to 15 ILA cores per control core JTAG Industry Best

® Advanced Debug Capabilities Using ChipScope ILA  Solves the debug bottleneck by —Enabling in-system analysis of any internal FPGA signal —While running at full system speed —Easing analysis of any package pins (BGA)  ChipScope ILA —Enabled by powerful capture and control ILA cores —Silicon based solution enables analysis at system speeds —Extensive memory enables comprehensive data capture —Unique design / flow enables flexible trigger conditions —ILA PROBE enables ILA modification without re-layout

® HDL Source Management Part Of Alliance Series Design Manager Industry First  Archives design source files with design versions and revisions  Answers the question: Can you tell me which HDL source created this bitstream?

® The Industry’s Best Partnerships  Xilinx EDA Alliance program delivers the most advanced design flows / best quality of results —Incremental design with Exemplar, Synopsys, and Synplicity —Board level verification using STAMP and LMG SmartModels  OEM with Synopsys delivers Xilinx exclusive B.L.I.S. (Block Level Incremental Synthesis) —Included in Synopsys FPGA Compiler II and FPGA Express (part of Foundation Series solutions)  OEM with MTI enabling VITAL accelerated simulation (and secure IP?) Partnerships

® Xilinx Software Vision  Help our customers succeed with their Xilinx design —Focus on runtime, design speed, and software before silicon  Improve our customers design flows —Make Xilinx design flows easier than all others —Improve integration with third party EDA vendors —Drive EDA Alliance partner innovation “Xilinx software vision is to enhance our customers ability to take advantage of the time to market benefits of using Xilinx logic devices.” Rich Sevcik, Sr. VP ISSG

® Benchmark Information v3.1i vs. Quartus

® Performance Comparison of 3.1i vs. Quartus 25% Quartus ‘extra’ 15%  Quartus —Only four designs improved with constraints (out of 28 designs) — Three designs won’t run due to clock skew! Performance Comparison 3.1i results are faster in either mode Quartus ‘normal’ Of VIRTEX-E -8 vs. APEX E-1

® Runtime Comparison of 3.1i vs. Quartus V3.1i Non-Timing Driven Runtime Advantage V3.1i Timing Driven Runtime Advantage

® ChipScope vs. SignalTap

® ChipScope ILA vs. ASIC tools  Embedded logic analysis is not efficient or easily accomplished in an ASIC —Must be fabricated onto the die during the prototype cycle  Can’t be changed once implemented —ASIC prototypes must be re-spun to remove or change logic analysis cores