1. ChipScope Pro Software

2. What Engineers are Saying
FPGA designs are becoming more complex
Designs are becoming faster
Design times are becoming shorter
Debugging and verification are more challenging
Debugging and verification consume a significant portion of FPGA design time
An FPGA design survey conducted by Xilinx indicates that FPGA debugging and verification accounts for nearly 50% of the FPGA design time
Debugging and verification need to be easier and integrated into the FPGA design flow

3. Logic of Debugging Modify design Probe design Analyze debugging data
Identify fix
Verify design
Create design
Debugging is problem solving
Break a problem into basic parts
Remove or reduce variables and variation
Predict and verify
Debugging is an iterative process
Verification is a component of debugging
Confirming no problems remain
Reconfigurable nature of FPGAs enables
an iterative debugging process

4. ChipScope Shortens Debugging
Works the way you solve problems
Divide a problem into basic parts
Remove variation introduced by external debugging solutions
Enables a very fast, iterative process of prediction and verification
Provides what you have requested
Reduction of debugging and verification time
A powerful tool that is easy to use
Focus on solving the problem, not on learning the tool
Integrated part of the Xilinx FPGA design flow
Final Device
Design
Implementation
Specification
20% of
Time
ChipScope™ Pro
On-Chip Verification
and Debugging
40%
Shrink overall design
time by 25%

5. The ChipScope Pro Software
Use the ChipScope Pro software for
Verification and debug
Injecting short signal sequences
Capturing data for post-bench analysis
Do Not Use ChipScope Pro for
A replacement for a simulation tool
Accessing the System Monitor
Testing high-speed I/O
Remote diagnostics/monitoring

6. Optimized Debugging Cores
Virtual Input/Output (VIO) Core
Virtual inputs and outputs
Stimulate logic with pulse trains
Virtual Input/Output (VIO) Core
Virtual inputs and outputs
Stimulate logic with pulse trains
Aurora
OPB SDRAM
User Logic
PLB Bus
OPB Bus
Bridge
OPB GPIO
Arbiter
Virtual Input/Output (VIO) Core
Virtual inputs and outputs
Stimulate logic with pulse trains
Virtual Input/Output (VIO) Core
Virtual inputs and outputs
Stimulate logic with pulse trains

7. Core Resources ChipScope™ Pro software cores utilize FPGA resources
For what?
Block RAM: trigger and data storage
Slice logic: trigger comparisons
You must leave room for the ChipScope Pro software cores in the FPGA
This may require using a larger part in the same package as you will use in production
The CORE Generator and Core Inserter tools can estimate block RAM usage, but the design may still end up with too many block RAMs
If MAP issues an error, reduce the number of observed signals or the sample data depth to reduce block RAM usage
Must be able to route signals to the core
No physical pin signals available

8. Using ChipScope Pro Software
Place ChipScope™ Pro cores into the design
Attach internal nodes for viewing to the ChipScope Pro core
Generate the ChipScope Pro cores by using the Core Generator, Core Inserter tool, or PlanAhead software
Place and route the design with the Xilinx ISE™ implementation software tools
Download the bitstream to the device under test and analyze the design with the ChipScope Pro software
Core Or Core
Generator Inserter
ChipScope Pro
Core Generator
Instantiate Cores into
Source HDL
Connect Internal Signals
to Core (in Source HDL)
Synthesize
Implement
ChipScope Pro Core
Inserter (into netlist)
Download and debugging
Using ChipScope Pro software

9. Adding the ChipScope Pro Cores
Use the icon or click ProjectNew Source
Select ChipScope Definition and Connection File (CDC)
Specify a name for the core
Only one CDC file is allowed in the project at a time
But multiple CDC files can be stored in the working directory

10. The ICON Core
ICON (Integrated Control) core: This core controls up to 15 capture cores
The ICON core interfaces between the JTAG interface and the capture cores
Capture cores: Customizable cores for creating triggers and data storage
Customizable number, width, and storage of trigger ports
ILA (Integrated Logic Analyzer) core: Capture core for HDL designs
ATC2 (Integrated Logic Analyzer with Agilent Trace) core: similar to the ILA core, except data is captured off-chip by the Agilent Trace Port Analyzer
IBA/OPB (Integrated Bus Analyzer for CoreConnect On-Chip Peripheral Bus) core: Capture core for debugging CoreConnect OPB
IBA/PLB (Integrated Bus Analyzer for CoreConnect Processor Local Bus) core: Similar to the IBA/OPB core, except for the PLB bus
VIO (Virtual Input/Output core): Define and generate virtual I/O ports

11. The ILA Core User-selectable, one to four trigger ports
Up to 256 channels per trigger port
Multiple match units on the same trigger port
Up to 16 match units (For example, 4 trigger ports, 4 match units each = 16 match conditions)
Trigger condition sequencer
Defines complex trigger sequences that include up to 16 states or levels

12. Things to Know About ILA Cores
Integrated Logic Analyzer (ILA) cores can be added with either the CORE Generator or Core Inserter tools or PlanAhead tool
A design can contain up to 15 ILA cores
Maximum speed of the ILA core varies according to device family and selected features
Turning on more “features” generally slows down the performance of the core and causes it to consume additional fabric resources

13. ChipScope Pro Software VIO Core
Insert virtual pins into your design using VIO
Inputs are virtual LEDs
Driven by internal FPGA signals
Different refresh rates are available
Outputs are virtual DIP switches
Force value or pulse train into the FPGA
VIO core can be defined
Input or output
Synchronous or asynchronous
System clock or JTAG clock
Up to 256 bits each

14. Things to Know About VIO Cores
Can only be created by the CORE Generator tool
Uses no block RAM, only logic
Inputs are like LEDs for examining signals
Outputs are switches or pushbuttons for driving signals

15. Core InserterFlow
Core Inserter inserts cores directly into the netlist
HDL code is untouched
Only post-synthesis nodes are available
Bypass this tool to remove cores
Inserter must perform the first portion of translate
Core generation and insertion are done together
ChipScope Pro Core Inserter tool is run from within Project Navigator/PlanAhead
CORE Generator
Synthesize
Instantiate Cores into
Source HDL
ChipScope Pro Core
Inserter (into netlist)
Connect Internal Signals
to Core (in Source HDL)
Synthesize
Implement
Download and Debug
Using ChipScope Pro Software

16. Things to Know About the Core Inserter and PlanAhead Flows
It is strongly recommended to set the synthesis option for “keep hierarchy” to “yes” or “soft”
Preserves the netlist hierarchy which makes it easier to locate signals for debugging
Enables filtering according to the design hierarchy
Design implementation will take an extra 2-3 minutes to generate the cores for the ICON and a single ILA
Only required if new cores are added or existing cores modified
The PlanAhead and Inserter flows are not compatible with the Core Generator flow
This flow is not available when in ISE Integration mode
Pre-existing debug cores may be viewed, but not changed
Only the ChipScope Pro ICON and ILA cores may be created and connected using the Inserter flow
Probing inside NGC core files is prohibited
Only interface signals are accessible
PlanAhead 12, ISE 12, and ChipScope Pro 12 tools must be used with this flow
Mixing and matching tool versions is not supported

17. CORE Generator Tool Flow
Generate cores that are instantiated directly into the HDL
Allows access to all HDL nodes
Requires changes to the code
Must comment out cores to remove them
Uses standard implementation flow
Core generation and insertion done separately
Core Generator tool can also be launched from latest 12.1 PlanAhead
CORE Generator
Synthesize
Instantiate Cores into
Source HDL
ChipScope Pro Core
Inserter (into netlist)
Connect Internal Signals
to Core (in Source HDL)
Synthesize
Implement
Download and Debug
Using ChipScope Pro Software

18. CORE Generator versus CORE Inserter
© Copyright 2012 Xilinx

19. Summary Shorten debug time
Break the problem into manageable parts
ChipScope™ Pro software enables rapid iteration
Add ChipScope Pro software cores at any time
Debug in three simple steps
Specialized cores allow you to focus on solving problems
ILA for viewing results
VIO for driving changes
Minimal impact to FPGA design
Design at system speed
Optimized cores consume minimal FPGA resources