Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-1 Lecture 14 CMOS Logic Gates Feb. 5, 2003

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-2 Contents of the Course ASICFPGA n Transistor and Layout n Gate and Schematic n Systems and VHDL/Verilog

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-3 Contents of the Course (cont’d) 2 ASIC labs2 FPGA labs n Transistor/Layout n Gate and Schematic n Systems/VHDL (Cadence) (Synopsys) (Xilinx Foundation)

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-4 Topics n Combinational logic functions. n Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-5 Combinational logic expressions n Combinational logic: function value is a combination of function arguments. n A logic gate implements a particular logic function. n Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-6 Gate design Why designing gates for logic functions is non-trivial: –may not have logic gates in the libray for all logic expressions; –a logic expression may map into gates that consume a lot of area, delay, or power.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-7 Boolean algebra terminology n Function: f = a’b + ab’ n a is a variable; a and a’ are literals. n ab’ is a term. n A function is irredundant if no literal can be removed without changing its truth value.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-8 Completeness n A set of functions f1, f2,... is complete iff every Boolean function can be generated by a combination of the functions. n NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. n Transmission gates are not complete. n If your set of logic gates is not complete, you can’t design arbitrary logic.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-9 Static complementary gates n Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. n Static: do not rely on stored charge. n Simple, effective, reliable; hence ubiquitous.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-10 Static complementary gate structure Pullup and pulldown networks: pullup network pulldown network V DD V SS out inputs

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-11 Inverter a out +

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-12 Inverter layout (tubs not shown) a out + transistors GND VDD aout tub ties

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-13 NAND gate + b a out

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-14 NAND layout + b a out b a VDD GND tub ties

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-15 NOR gate + b a out

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-16 NOR layout b a out a b VDD GND tub ties

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-17 Pullup/pulldown network design n Pullup and pulldown networks are duals. n To design one gate, first design one network, then compute dual to get other network. n Example: design network which pulls down when output should be 0, then find dual to get pullup network.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-18 Lectures 15 Transfer Characteristics (Transfer Curve and Noise Margin) Feb. 7, 2003

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-19 Topics n Electrical properties of static combinational gates: –Noise margin and transfer curve; –delay; –power.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-20 Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-21 Logic level matching n Levels at output of one gate must be sufficient to drive next gate.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-22 Transfer characteristics n Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-23 Inverter transfer curve

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-24 Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sized—in this case, high pullup resistance leads to smaller logic 1 range.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-25 Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t=  voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS.

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-26 Example 1 Transfer curve and noise margin

Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week5-27