Download presentation
Presentation is loading. Please wait.
1
1 Contents Reviewed Rabaey CH 3, 4, and 6
2
2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_2.jpg "2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
3
3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_3.jpg "3 The PMOS Transistor [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
4
4 The CMOS Technology [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
5
5 Threshold Voltage Concept [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
6
6 Current-Voltage Relations [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
7
7 Transistor in Saturation [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
8
8 2-D Representation of MOS Transistor [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
9
9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_9.jpg "9 Switch-Level View of NMOS & PMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
10
10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_10.jpg "10 CMOS Switch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
11
11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_11.jpg "11 CMOS Inverter [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
12
12 CMOS Inverter Layout Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m =2 [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
13
13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_13.jpg "13 NMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
14
14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_14.jpg "14 PMOS Switches in Series [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
15
15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_15.jpg "15 Switches in Parallel [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
16
16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_16.jpg "16 2-Input CMOS NAND Gate: the Switch View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
17
17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_17.jpg "17 2-Input CMOS NAND Gate: the Circuit View [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
18
18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_18.jpg "18 N-input CMOS NAND Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
19
19 4-Input NAND Gate In1In2In3In4 Vdd GND Out [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
20
20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_20.jpg "20 2-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
21
21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_21.jpg "21 N-Input CMOS OR-Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
22
22 Properties of CMOS Gates Vdd and GND are never directly connected i.e. no shorting Output is always connected to either Vdd or GND i.e. it never floats
23
23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_23.jpg "23 Making Compound Gates in CMOS F = ((A.B) + (C.D)) [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
24
24 Key Idea in CMOS Compound Logic Gates [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
25
25 More on CMOS Logic Style [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
26
26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_26.jpg "26 Pull-Up and Pull-Down Circuits [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
27
27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_27.jpg "27 CMOS Compound Gate [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
28
28 What is this? [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![28 What is this [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_28.jpg "28 What is this [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
29
29 How do we implement these? Z = (A.B.C.D)’ Z = ((A.B) + C.(A+B))’ Z = A.B + A’.B’ what is this? Z = A.B’.C’ + A’.B’.C + A’.C’.B + A.B.C what is this?
30
30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_30.jpg "30 A 2-Input CMOS Multiplexer Output = A.S + B.S’ [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
31
31 How can one implement multiplexer using CMOS gates?
32
32 Layout: the Standard Cell Approach [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
33
33 Two versions of a.(b+c) [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
34
34 Logic Graph [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
![34 Logic Graph [Adapted from Copyright 1996 UCB]](http://images.slideplayer.com/27/9049214/slides/slide_34.jpg "34 Logic Graph [Adapted from Copyright 1996 UCB]")
35
35 Consistent Euler Path [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
36
36 Example: x = ab + cd [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
37
37 Existence of Consistent Euler Paths May depend on the way the Boolean expression is written Example: x = (A + B.C + D.E)’ has no consistent Euler paths But, x = (B.C + A + D.E)’ does
38
38 Memory & Storage in CMOS
39
39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
![39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]](http://images.slideplayer.com/27/9049214/slides/slide_39.jpg "39 A CMOS Positive Level- Sensitive D Latch [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]")
40
40 A CMOS Positive Edge- Triggered D Register
41
41 Performance Analysis of CMOS Gates
42
42 MOS Transistors are not “ Ideal ” Switches [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
43
43 CMOS Inverter: A More Detailed View [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
44
44 CMOS Inverter: Steady State Response [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
45
45 CMOS Inverter: Transient Response [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
46
46 What is the value of R on ? [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
47
47 Numerical Examples for 1.2 m CMOS [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
48
48 Transistor Sizing [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
![48 Transistor Sizing [Adapted from Copyright 1996 UCB]](http://images.slideplayer.com/27/9049214/slides/slide_48.jpg "48 Transistor Sizing [Adapted from Copyright 1996 UCB]")
49
49 Propagation Delay Analysis [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
50
50 Analysis of Propagation Delay [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
51
51 Design for Worst Case [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
52
52 Influence of Fan-in and Fan-out on Delay [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
53
53 t p as a Function of Fan-in [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
54
54 Fast Complex Gates - I [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
55
55 Fast Complex gates - II [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
56
56 Fast Complex Gates - III [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
57
57 Fast Complex Gates - IV [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
58
58 Example: Full Adder [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
59
59 Revised Full Adder [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
Similar presentations
![COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]](/7/1652107/big_thumb.jpg "COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]>")
