1. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

2. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

3. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

4. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

5. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

6. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

7. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

8. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

9. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

10. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

11. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

12. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

13. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

14. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

15. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

16. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Fanout n Fanout adds capacitance. source sink

17. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Ways to drive large fanout n Increase sizes of driver transistors. Must take into account rules for driving large loads. n Add intermediate buffers. This may require/allow restructuring of the logic.

18. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Buffers

19. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Wire capacitance n Use layers with lower capacitance. n Redesign layout to reduce length of wires with excessive delay.

20. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Placement and wire capacitance unbalanced load more balanced dvr g1 g2 g3 g4 dvr g1 g2 g3 g4

21. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Path delay n Combinational network delay is measured over paths through network. n Can trace a causality chain from inputs to worst-case output.

22. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

23. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Critical path n Critical path = path which creates longest delay. n Can trace transitions which cause delays that are elements of the critical delay path.

24. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Delay model n Nodes represent gates. n Assign delays to edges - signal may have different delay to different sinks. n Lump gate and wire delay into a single value.

25. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Critical path through delay graph

26. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Reducing critical path length n To reduce circuit delay, must speed up the critical patheducing delay off the path doesn’t help. n There may be more than one path of the same delay. Must speed up all equivalent paths to speed up circuit. n Must speed up cutset through critical path.

27. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Transistor sizing n Effective resistance depends on transistor W/L - less delay means wider transistors. n For equal pullup and pulldown times, W/L of pullup and pulldown obey Kp/Kn.

28. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR

29. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Logic transformations n Can rewrite by using subexpressions. n Flattening logic increases gate fanin. n Logic rewrites may affect gate placement.

30. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR False paths n Logic gates are not simple nodes - some input changes don’t cause output changes. n A false path is a path which cannot be exercised due to Boolean gate conditions. n False paths cause pessimistic delay estimates.

31. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR False path example

32. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Logic optimization n Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library. n Optimization goals: minimize area, meet delay constraint.

33. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Technology-independent optimizations n Works on Boolean expression equivalent. n Estimates size based on number of literals. n Uses factorization, resubstitution, minimization, etc. to optimize logic. n Technology-independent phase uses simple delay models.

34. Modern VLSI Design 2e: Chapter4 Copyright  1998 Prentice Hall PTR Technology-dependent optimizations n Maps Boolean expressions into a particular cell library. n Mapping may take into account area, delay. n May perform some optimizations on addition to simple mapping. n Allows more accurate delay models.