1. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-1 Lectures 21, 22 FPGA and Top-Down Design Flow Mar. 3 and 5, 2003

2. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-2 What is an FPGA ? Fully SRAM based configuration Input/Output Blocks (IOB) Block Memory. Configurable Logic Blocks (CLB) — Used to form adders, accumulators, multipliers, etc.

3. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-3 What a Range of Devices: Which One?  The father device from which all Virtex devices have been derived — Rarely used for new designs — 384 to 6144 CLBs with up to 128k-bits RAM  The lowest cost devices for DSP applications ($5 to $10) — 96 to 864 CLBs with up to 48k-bits RAM Cont’d on next slide

4. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-4 What a Range of Devices: Which One?  384 to 16224 CLBs with up to 832k-bits RAM  For those particularly memory intensive algorithms — 2400 to 4704 CLBs with up to 1120k-bits RAM  128 to 23,296 CLBs* with up to 3024k-bits RAM — Latest family and most DSP-focused FPGA architecture ever to be released *scaled to enable comparison

5. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-5 Xilinx FPGA Device Architecture Digital Clock Management Blocks (DCM) Memory Blocks Configurable Logic Blocks (CLB) Input/Output Blocks (IOB) Fully programmable. Replace all functionality in <50ms Programmable Interconnect  Uniform structure of programmable blocks, which can be connected together using programmable interconnect

6. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-6 Spartan-II —Memory blocks are located down each side of the device – Each memory block is 4 CLBs high —Since the area of CLBs increases more than the length of the two edges, the CLB to block memory ratio increases with larger devices XC2S15 = 24 CLB per Block RAM XC2S150 = 72 CLB per Block RAM  Spartan-II geared to high volume production

7. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-7 Contents of the Course ASICFPGA n Transistor and Layout n Gate and Schematic n Systems and VHDL/Verilog

8. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-8 Contents of the Course (cont’d) 2 ASIC labs2 FPGA labs n Transistor/Layout n Gate and Schematic n Systems/VHDL (Cadence) (Synopsys) (Xilinx Foundation)

9. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-9 Xilinx Foundation Tutorial Lab 3: Top-down design Lab 4: Download to FPGA development board

10. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-10 Lecture 23 Driving Large Load Pass Logic Mar. 7, 2003

11. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-11 Driving large loads n Sometimes, large loads must be driven: –off-chip; –long wires on-chip. n Sizing up the driver transistors only pushes back the problem—driver now presents larger capacitance to earlier stage.

12. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-12 Cascaded driver circuit

13. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-13 Optimal sizing n Use a chain of inverters, each stage has transistors a larger than previous stage. n Minimize total delay through driver chain: –t tot = n(C big /C g ) 1/n t min. n Optimal number of stages: –n opt = ln(C big /C g ). Driver sizes are exponentially tapered with size ratio .

14. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-14 Example 1

15. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-15 Topics n Swtich logic.

16. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-16 Switch logic n Can implement Boolean formulas as networks of switches. n Can build switches from MOS transistors— transmission gates. n Transmission gates do not amplify but have smaller layouts.

17. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-17 Types of switches

18. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-18 Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: –conducts logic 0 perfectly; –introduces threshold drop into logic 1. V DD V DD - V t

19. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-19 n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels. V DD V DD - V t

20. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-20 n-type switch driving switch logic Voltage drop causes next stage to be turned on weakly. V DD V DD - V t V DD

21. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-21 Behavior of complementary switch n Complementary switch products full-supply voltages for both logic 0 and logic 1: –n-type transistor conducts logic 0; –p-type transistor conducts logic 1.

22. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-22 Layout characteristics n Has two source/drain areas compared to one for inverter. n Doesn’t have gate capacitance.

23. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-23 Example 2

24. Modern VLSI Design 3e: Chapter 3Partly from 2002 Prentice Hall PTR week9-24