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Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003.

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Presentation on theme: "Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003."— Presentation transcript:

1 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-1 Lectures 6, 7 and 8 Transistor Function Jan. 17, 20 and 22, 2003

2 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-2 Topics n Previous: –Transistor as switch –Basic fabrication steps. n Basic Transistor function n Basic transistor behavior.

3 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-3 Transistor structure n-type transistor:

4 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-4 Gate voltage and the channel gate drainsource IdId gate drainsource V gs > = V t V gs < V t Vt= 0.7 V Vs=0 V

5 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-5 Drain current characteristics

6 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-6 Example 1 n V gs keeps 1.5V, 2.5V, 5V n V ds changes

7 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-7 Drain current n Linear region (V ds < V gs - V t ): !!! –I d = k’ (W/L)[(V gs - V t )V ds - 0.5 V ds 2 )] n Saturation region (V ds >= V gs - V t ): –I d = 0.5k’ (W/L)(V gs - V t ) 2 Text book is wrong!!!

8 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-8 What is related to the characteristics n W/L ratio!!! n V between Drain and Source n V between Gate and Source n Threshold voltage n Material

9 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-9 Transistor layout n-type (tubs may vary): w L

10 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-10 0.5  m transconductances From a MOSIS process: n n-type: –k n ’ = 73  A/V 2 –V tn = 0.7 V n p-type: –k p ’ = 21  A/V 2 –V tp = -0.8 V

11 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-11 Current through a transistor Use 0.5  m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. n V gs = 2V: I d = 0.5k’(W/L)(V gs -V t ) 2 = 93  A n V gs = 5V: I d = 1 mA

12 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-12 Explanation n When V gs = 2V, can current go beyond 93 uA (when V ds changes)?

13 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-13 Example 2 n When Vgs = 2 V and V ds = 2 V and 1.2 V respectively, calculate the I ds? –W/L = 8 –K’n= 73 uA/V^2

14 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-14 Example 3 n Inverter: when transition time, what is the current? (important example) –How N and P work? n Inverter: after transition time, what is the current?

15 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-15 Questions n What is the real carrier in N transistor?

16 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-16 Gate voltage and the channel gate drainsource IdId gate drainsource V gs > = V t V gs < V t Vt= -0.8 V Vs=5 V

17 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-17 Questions n What is the real carrier in P transistor?

18 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-18 Transistor and digital Logic n Combinational logic –Depend on transistor & inverter n Sequential logic –Depend on transistor & inverter

19 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-19 Drain current characteristics

20 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-20 Review n N and P transistors as switches n Fabrication process n Current Characteristics of N and P transistors

21 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-21 Example 4

22 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-22 Lecture 9 Transistor Parasitics & Latch Up Jan. 24, 2003

23 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-23 Topics n Transistor and basic fabrication steps. n Basic Transistor function n Basic transistor behavior. n Latch up.

24 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-24 Basic transistor parasitics n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance.

25 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-25 Basic transistor capacitance n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. –C gs = C ol W n Gate/bulk overlap capacitance.

26 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-26 Transistor gate capacitance n Gate-source/drain overlap capacitance: gate sourcedrain overlap

27 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-27 Transistor source/drain parasitics n Source/drain have significant capacitance, resistance. n Measured same way as for wires. n Source/drain R, C may be included in Spice model rather than as separate parasitics.

28 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-28 Transistor Resistance n R=U/I n Future topic

29 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-29 Latch-up n CMOS ICs have parasitic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

30 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-30 Parasitic SCR circuitI-V behavior

31 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-31 Parasitic SCR structure

32 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-32 Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

33 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-33 Tub tie layout metal (V DD ) p-tub p+

34 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-34 Question Why these tub ties are needed?

35 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-35

36 Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week3-36


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