1. 1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology

2. H.-H. S. Lee 2 CMOS Inverter Connect the following terminals of a PMOS and an NMOS Gates Drains V in V out V dd Gnd V out V in V in = HIGH V out = LOW (Gnd) ON OFF V dd Gnd V out V in V in = LOW V out = HIGH (V dd ) ON OFF V dd PMOS Ground NMOS

3. H.-H. S. Lee 3 CMOS Voltage Transfer Characteristics V dd Gnd V in V out PMOS NMOS OFF: V_GateToSource < V_Threshold LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource Note that in the CMOS Inverter  V_GateToSource = V_in

4. H.-H. S. Lee 4 Pull-Up and Pull-Down Network CMOS network consists of a Pull- UP Network (PUN) and a Pull- Down Network (PDN) PUN consists of a set of PMOS transistors PDN consists of a set of NMOS transistors PUN and PDN implementations are complimentary to each other PMOS  NOMS Series topology  Parallel topology …. I0I0 I1I1 I n-1 OUPTUT V dd PUN Gnd PDN

5. H.-H. S. Lee 5 PUN/PDN of a CMOS Inverter AB 01 1Z AB 0Z 10 AB 01 10 Pull-Up Network Pull-Down Network Combined CMOS Network V dd A Gnd B CMOS Inverter

6. H.-H. S. Lee 6 Gate Symbol of a CMOS Inverter V dd A Gnd B CMOS Inverter AB B = Ā

7. H.-H. S. Lee 7 PUN/PDN of a NAND Gate ABC 001 011 101 11Z ABC 00Z 01Z 10Z 110 Pull-Up Network Pull-Down Network V dd A B A B C

8. H.-H. S. Lee 8 PUN/PDN of a NAND Gate ABC 001 011 101 11Z ABC 00Z 01Z 10Z 110 ABC 001 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network V dd A B A B C

9. H.-H. S. Lee 9 NAND Gate Symbol ABC 001 011 101 110 V dd A B A B C A B C Truth Table

10. H.-H. S. Lee 10 PUN/PDN of a NOR Gate ABC 001 01Z 10Z 11Z ABC 00Z 010 100 110 Pull-Up Network Pull-Down Network V dd A C B A B

11. H.-H. S. Lee 11 PUN/PDN of a NOR Gate ABC 001 01Z 10Z 11Z ABC 00Z 010 100 110 ABC 001 010 100 110 Pull-Up Network Pull-Down Network Combined CMOS Network A C B A B V dd

12. H.-H. S. Lee 12 NOR Gate Symbol ABC 001 010 100 110 A B C Truth Table A C B A B V dd

13. H.-H. S. Lee 13 How about an AND gate V dd A B A Gnd C NAND Inverter B C = A B A B C

14. H.-H. S. Lee 14 An OR Gate A B A B V dd Gnd C Inverter NOR A B C

15. H.-H. S. Lee 15 What’s the Function of the following CMOS Network? V dd C ABC 00Z 011 101 11Z ABC 000 01Z 10Z 110 ABC 000 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR

16. H.-H. S. Lee 16 Yet Another XOR CMOS Network V dd C ABC 00Z 011 101 11Z ABC 000 01Z 10Z 110 ABC 000 011 101 110 Pull-Up Network Pull-Down Network Combined CMOS Network XOR Function = XOR

17. H.-H. S. Lee 17 Exclusive-OR (XOR) Gate V dd C ABC 000 011 101 110 A B C Truth Table

18. H.-H. S. Lee 18 XNOR How about XNOR Gate ABC 001 010 100 111 A B C Truth Table How do we draw the corresponding CMOS network given a Boolean equation?

19. H.-H. S. Lee 19 XNOR How about XNOR Gate ABC 001 010 100 111 A B C Truth Table V dd C XOR Inverter

20. H.-H. S. Lee 20 A Systematic Approach Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN PUN Draw PUN using PMOS based on the Boolean eqn ANDseries AND operation drawn in series ORparallel OR operation drawn in parallel variable Invert each variable of the Boolean eqn as the gate input for each PMOS in the PUN PDN Draw PDN using NMOS in complementary form Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

21. H.-H. S. Lee 21 Example 1 In series In parallel Vdd (1) Draw the Pull-Up Network

22. H.-H. S. Lee 22 Example 1 In series In parallel Vdd (2) Assign the complemented input A C B

23. H.-H. S. Lee 23 Example 1 In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A C

24. H.-H. S. Lee 24 Example 1 In series In parallel Vdd (3) Draw the Pull-Down Network in the complementary form A C B A CB

25. H.-H. S. Lee 25 Example 1 In series In parallel Vdd Label the output F A C B A CB F

26. H.-H. S. Lee 26 Example 1 In series In parallel Vdd A C B A CB F ABCF 0000 0010 0101 0111 1001 1010 1101 1111 Truth Table

27. H.-H. S. Lee 27 An Alternative for XNOR Gate ABC 001 010 100 111 A B C Truth Table V dd C

28. H.-H. S. Lee 28 Example 3 Start from the innermost term A B D AC A D

29. H.-H. S. Lee 29 Example 3 Start from the innermost term A B D AC A D A C

30. H.-H. S. Lee 30 Example 3 Start from the innermost term A B D AC A D A C B

31. H.-H. S. Lee 31 Example 3 Start from the innermost term A B D AC A D A C B Vdd F Pull-Up Network Pull-Down Network

32. H.-H. S. Lee 32 Example 4 Start from the innermost term A B D A C A D A C B Vdd F E D E D Pull-Down Network Pull-Up Network

33. H.-H. S. Lee 33 Another Example How ??