COMPUTER ORGANIZATION CSCE 230 Final Project

OVERVIEW  Implemented RISC processor  VHDL  Test program created to demonstrate abilities

COMPONENTS  ALU – Made in lab  Register File – Made in lab  Datapath  Connection of components  5 stages  Control Unit  Controls processor  Uses signals  Instruction Address Generator  Uses adder & two multiplexors to increment  Processor Memory Interface  Fetches instructions & places in IR

INSTRUCTIONS  R-Type: Arithmetic  D-Type: Data & Immediate values  B-Type: Branches  J-Type: Jumps

BONUS - ASSEMBLER  Written in Java  All (R,D,B) instruction types supported  Syntax similar to Altera’s native language  Handles negative values  Loadi (J type supported)  Exports to.mif file

BONUS - LIGHTS  9 red LED’s  16 bit register to maintain output  4 to 16 decoder (HEX,LEDG,LEDR,SW,KEYS)  HEX Lights  16 bit register for maintain each

TEST PROGRAM – BINARY TO DECIMAL

OUR EXPERIENCE  Time  Debugging  VHDL  Compile Time