1. VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Chris.Erickson@auburn.edu

2. Objectives Logically perform the designed functions Be efficient –Code length –Routines –Signal utilization Perform the functions appropriately per cycle

3. Component Development All components designed & developed independently Instruction Register Instruction Register Program Counter Program Counter Register File Register File Data Register Data Register Multiplexers Multiplexers Test RS Test RT Test RD Test RegWrite Register File B A

4. Multicycle Datapath Cycles per instruction (CPI): Load Word5 Load Word5 Store Word4 Store Word4 Register-type4 Register-type4 Branch3 Branch3 Jump3 Jump3

5. 3 to 5 Cycles per instruction StepR-type (4 cycles) Mem. Ref. (4 or 5 cycles) Branch type (3 cycles) J-type Instruction fetch IR ← Memory[PC]; PC ← PC+1 Instruction decode/ Register fetch A ← Reg(IR[25-21]); B ← Reg(IR[20-16]) Execution, Branch & Jump completion ALUOut ← A op B ALUOut ← A+sign extend IR[15-0] If (A=B) then thenPC←ALUOut PC←PC[31- 26] & IR[25-0] Mem. Access or R-type completion Reg(IR[15-11]) ← ALUOut MDR←M[ALUout] or M[ALUOut]←B Memory read completion Reg(IR[20-16]) ← MDR

6. Control FSM Instruction decode ALU operation Write PC on branch condition Write memory data Write PC on jump Write register Read memory data Instruction fetch Compute memory addr. Write register lw or sw lw sw R B J Start State 0 1 23 45 6 7 89

7. Code Initialize, set state = 0 If state = 0 then Set state 0 signals Set state = 1 for next clock cycle If state = 1 then Set state 1 signals Set state = 2 for next clock cycle If state = 2, depending on opcode, we will either go down path of register-type, load word, store word, branch, or jump instruction.

8. Cycle Boundaries Multiplexers are handled at the end of each cycle Multiplexer outputs serve as “variables” to be used as inputs for the next clock cycle Either a multiplexer or another stand-alone component must have a steady-state output to serve as input for the next cycle

9. Multicycle Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Memory Addr. Data 1 Sign extend Shift left 2 Opcode 31-25 0-15 20-16 25-21 Shift left 2 25-0 28-31 15-11

10. Completed !! Any Question? Comments?