1. 1 CS/COE0447 Computer Organization & Assembly Language Chapter 5 Part 2

2. 2 Fig 5.17

3. 3 Control Unit Implements (in hardware) an if statement: –If opcode == 000000 # r-type instruction MemWrite = 0 MemRead = 0 MemToReg = 0 … # values assigned for all the control unit’s output signals –Elif opcode == 0x23 # lw MemWrite = 0 MemRead = 1 MemToReg = 1 … –Elif opcode == 0x4 # beq MemWrite = 0 MemRead = 0 MemToReg = X # don’t care … –… # an Elif test for each opcode

4. 4 Examples In Lab 10, you did examples for an R-type instruction and for sw Now, let’s look at examples for beq and lw

5. 5 Instruction Execution (reminder) beq –Fetch instruction and add 4 to PC beq $t0,$t1,L Assume that L is +3 instructions away –Read two source registers $t0,$t1 –Sign Extend the immediate, and shift it left by 2 0x0003  0x0000000c –Perform the test, and update the PC if it is true If $t0 == $t1, the PC = PC + 0x0000000c [we will follow what Mars does, so this is not Immediate == 0x0002; PC = PC + 4 + 0x00000008]

6. 6 Fig 5.17 0x10010000: Beq $t0,$t1,L L == 1001000c 000100

7. 7 Example: lw r8, 32(r18) Let’s assume r18 has 1,000 Let’s assume M[1032] has 0x11223344 I-Format

8. 8 Example: lw r8, 32(r18) 35 18 8 0 32 1000 1032 0x11223344 (PC+4) MemRead RegWrite Branch=0 RegDest=0 ALUSrc=1 8 32 MemtoReg=1

9. 9 Control Sequence for lw OPcode = 35 –RegDst = 0 –ALUSrc = 1 –MemtoReg = 1 –RegWrite = 1 –MemRead = 1 –MemWrite = 0 –Branch = 0 –ALUop = 0

10. 10 Fig 5.17 (for reference)

11. 11 Control Signal Table Fig 5.18 Figure 5.18 shows the control-signal information for Fig 5.17. Figure 5.16 describes each of these signals, with one mistake: “PCSrc” in 5.16 should be “Branch”

12. 12 ALU Control HERE!! Depending on instruction, we perform different ALU operations Example –lw or sw: ADD –and: AND –beq: SUB ALU control input (3 bits) (page 301) –000: AND –001: OR –010: ADD –110: SUB –111: SET-IF-LESS-THAN (similar to SUB)

13. 13 ALU Control (figure 5.12) ALUop –00: lw/sw, 01: beq, 10: arithmetic, 11: jump

14. 14 ALU Control Truth Table Fig 5.13

15. 15 ALU Control Logic Design we’ll return to this when we cover appendix B

16. 16 Datapath w/ Jump Fig 5.24

17. 17 What We Have Now Fig 5.24

18. 18 Functional Units Used

19. 19 Single-Cycle Execution Timing (in pico-seconds)

20. 20 Single-Cycle Exe. Problem The cycle time depends on the most time- consuming instruction –What happens if we implement a more complex instruction, e.g., a floating-point mult. –All resources are simultaneously active – there is no sharing of resources We’ll adopt a multi-cycle solution –Use a faster clock –Allow different number of clock cycles per instruction

21. 21 A Multi-cycle Datapath A single memory unit for both instructions and data Single ALU rather than ALU & two adders Registers added after every major functional unit to hold the output until it is used in a subsequent clock cycle

22. 22 Multi-cycle Approach Reusing functional units –Break up instruction execution into smaller steps –We’ll need more and expanded MUX’s At the end of a cycle, keep results in registers –Additional registers Now, control signals are NOT solely determined by the instruction bits Controls will be generated by a FSM!