1 Controllers-system for APS – CubeSat nano-satellite Instructor: Daniel Alkalay Students: Moshe Emmer & Meir Harar Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Presentation - Final

2 Agenda Project Goals – Second semester Architecture/Interface Implementation - Demo FSL FSM – watch dog Summary

3 Project Goals APS – Cubesat is a multidisciplinary project. It involves AE and EE disciplines. Main task is to build a distributed system-on- chip architecture, using heterogeneous processing units. Each processor performs a different task. A proprietary serial communication protocol is implemented between the processors. Scope is on architecture abstract level.

4 CubeSat - Architecture / FINAL GOAL SA I/F & Bat C/D- Control Battery Attitude System Sensors & actuators Magneto-meter מד שמש Rate Gyro מגנטו-טורקרים Engines Sensors Actuators Accurate Positioning System שעון אטומי APS & TLM TransCeiver Power Distribution Over-current control TLM TT+C Attitude Control On-Board Controllers uBlaze + pBlaze + State-Machines Power Control Telemetry S&AI/FS&AI/F Payload TLM

5 System implementation - DEMO

6 Hardware Microblaze_0 BRAM_0 I-LMB Cntrl D-LMB Cntrl UART RS -232 OPB I-LMB D-LMB … DIP_Switches_8Bit Led_7SEGMENT Push_Buttons_3Bit LEDs_8Bit OPB Tested and studied, not included in design Tested and studied - included in design L.M.B – Local Memory Bus Peripherals – OPB IP’s

7 MicroBlaze – Soft processor for FPGA MicroBlaze Core Block Diagram

8 UART Lite A module that attaches to the OPB. One transmit and one receive channel (full duplex). 16-character transmit FIFO and 16-character receive FIFO. Configurable baud rate. Parameters:

9 FSL (Fast Simplex Link) Bus Microblaze_0 Microblaze_1

10 Up to 8 master and slave FSL interfaces are available on the MicroBlaze soft processor. Supports both synchronous and asynchronous FIFO modes – allows the master and slave side of the FSL to clock at different rates. Provides an external control bit for annotating data being transmitted – can be used by the slave side interface for multiple purposes. For example, use the bit to indicate the start or end of the transmission of a frame. We used this bus to transfer data between three soft processors implemented on the same chip Technical Features FSL_a Master_aSlave_b Master_b Slave_a FSL_b Microblaze_0 Microblaze_1 FSL (Fast Simplex Link) Bus

11 System implementation - DEMO

12 FSM – watch dog extend system’s physical robustness Especially important in a SPACE environment  Creating an independent closed-loop algorithm, which verifies system’s Demands BEGIN CASE current_state IS WHEN reset => IF ((mic_0 AND mic_1 AND mic_2) = '1') THEN next_state IF (NOT ( mic_0 OR mic_1 OR mic_2 ) = '1') THEN next_state next_state next_state <= reset; END CASE; END PROCESS nextstate_proc;

13 System implementation - DEMO An implementation of 3 independent controllers (3x MicroBlaze) will be demonstrated. Each processor executes a different task (arithmetic task): Division, Subtraction and Addition. Demonstrating data transfer between three processors. One of them is connected to Hyper-Terminal (through UART). A special macro function was created in order to support multi- packets transfer between the processors (aerospace wise). A system-wide watch-dog test, using FSM, was implemented to monitor the ‘health’ of the processors. MSB – Print Screen from EDK

14 Summary Design must first start in the architecture abstract level, especially when using FPGA technology In a system of various tasks, each can be implemented by an independent controller, while all will be communicating according to a protocol, defined by the designers On 1 Virtex-4, FPGA chip, one can implement many independent processing units; such as MicroBlazes, PicoBlazes, FSMs and other hardware modules. All can carry out different tasks and exchange data using a Fast, simple method – FSL bus It is also possible to break one mission into N different processes, using N different cores and raising performance by N*100 % (upper bound value!)

15 Summary FSL is a FIFO, 1-way bus that can smoothly answer any communication needs of the processing units. It can be activated either under a non-blocking or a blocking regime. Each, of course has its own advantages and disadvantages. blocking is the simple way, giving fast and un-complex design Think of the endless opportunities! With a FPGA chip and a good understanding of the architecture one can gain boost in performance of a process by using parallel cores!

16 Summary A system using MicroBlaze and FSL links to communicate between them has been developed, and with the experiments tested it can be concluded that the FSL links are an ideal choice for exchanging data between processors due to their high speed data transfer rates Analysing the synthesis results, it is clear that what limits the number of processors in a multiprocessor design on FPGA is the amount of BlockRAM available, not the total size of the FPGA.

17 Summary Completely Meshed A completely meshed network is a network in which each node is connected to every other node in the network. It is a good way to reduce the traveling time of packets over a network, because data goes directly from sender to receiver, but its main disadvantage is that the number of links grows extremely quickly when the number of nodes is increased. A completely meshed network topology with MBlaze and FSL links will only be possible for just 9 MBlazes, because of the limitation of 8 FSL links for each MicroBlaze processor.

18 Summary Ring Network A ring network is a network in which each node in the network is connected to the following and the preceding node in the network, forming a ring. Data is passed from node to node until it reaches the destination node. With MBlaze and FSL links there will not be a size limit for the network, because each MBlaze would just use 2 FSL links. The main problem of this topology is that data transfers from two nodes that are far from each other are very time consuming.