1. Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Mid-Term Presentation Performed by: Roni Ruach Yoni Tzur Supervised by: Evgeny Fiksman Triple Processor Redundancy Voting Unit

2. MicroBlaze – The Fastest Soft Processor for FPGAs Virtex-II (-6) 125 MHz

3. Processor Core RISC 32-bit ALU, 32-bit data bus, 32-bit instruction word, 32 x 32 General Purpose Register file 3 - Stage Pipeline IF (instruction fetch stage) Decode EX (execution stage) All instructions take 1 EX clock cycle except Load/store (2 clock cycles) Multiply (3 clock cycles) Branches (3 clock cycles)

4. Hardware Architecture There are two special registers in Microblaze processor: Machine Status Register (MSR) contains the carry flag and enables for interrupts. MSR can be written to with an MTS instruction Writes to MSR are delayed one clock cycle. Program Counter (PC) It can be read by accessing RPC, It cannot be written to using an MTS instruction. Interrupts r14 ←  PC PC ←  0x00000010 MSR[IE] ←  0 Exceptions r17 ←  PC PC ←  0x00000008

5. Hardware Architecture – cont. 16-instruction pre-fetch buffer Resolves all pipeline hazards in HW: assembler writing is necessary only for pre-scheduled branch delay slots Interrupt handling 1 Interrupt port exists on the core. Interrupt latency: 4 clock cycles (1 for detecting interrupt + 3 for branch)

6. Busses Addr[0:31] It is valid only when AS is high. Byte_Enable[0:3] indicate which byte lanes of the data bus contain valid data. MicroBlaze supports LMB and OPB busses: LMB (Local Memory Bus) Connects directly (and exclusively) to Xilinx BlockRAMs Fast, operates at MicroBlaze core frequency (125 MHz)

7. Data_Write[0:31] It becomes valid when AS is high and goes invalid in the clock cycle Data_Read[0:31] valid on the rising edge of the clock when Ready is high. Clk All operations on the LMB are synchronous to the MicroBlaze core clock. OPB (On-chip peripheral bus) General Purpose IO Timer / Counter Block Watchdog Timer / Timebase Interrupt Controller OPB arbiter OPB BlockRAM controller Lite UART JTAG UART (for debugging purposes) External Memory Controller (FLASH / SRAM / EPROM) Ethernet 10/100 MAC *

8. General Purpose Input/Output The GPIO is a simple peripheral consisting of two registers and a multiplexer for reading register contents and the GPIO I/O signals. The GPIO block diagram is shown in the following figure:

9. Microblaze_0 BRAM_0I-LMB CntrlD-LMB Cntrl UART RS232 Microblaze_1 BRAM_1I-LMB CntrlD-LMB Cntrl LEDs OPB I-LMB D-LMB I-LMB D-LMB OPB